/* $FreeBSD: src/sys/dev/hifn/hifn7751reg.h,v 1.4 2004/03/10 10:10:46 phk Exp $ *//*	$OpenBSD: hifn7751reg.h,v 1.35 2002/04/08 17:49:42 jason Exp $	*//* * Invertex AEON / Hifn 7751 driver * Copyright (c) 1999 Invertex Inc. All rights reserved. * Copyright (c) 1999 Theo de Raadt * Copyright (c) 2000-2001 Network Security Technologies, Inc. *			http://www.netsec.net * * Please send any comments, feedback, bug-fixes, or feature requests to * software@invertex.com. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products *    derived from this software without specific prior written permission. * * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * Effort sponsored in part by the Defense Advanced Research Projects * Agency (DARPA) and Air Force Research Laboratory, Air Force * Materiel Command, USAF, under agreement number F30602-01-2-0537. * */#ifndef __HIFN_H__#define	__HIFN_H__/* * Some PCI configuration space offset defines.  The names were made * identical to the names used by the Linux kernel. */#define	HIFN_BAR0		PCIR_BAR(0)	/* PUC register map */#define	HIFN_BAR1		PCIR_BAR(1)	/* DMA register map */#define	HIFN_TRDY_TIMEOUT	0x40#define	HIFN_RETRY_TIMEOUT	0x41/* * PCI vendor and device identifiers * (the names are preserved from their OpenBSD source). */#define	PCI_VENDOR_HIFN		0x13a3		/* Hifn */#define	PCI_PRODUCT_HIFN_7751	0x0005		/* 7751 */#define	PCI_PRODUCT_HIFN_6500	0x0006		/* 6500 */#define	PCI_PRODUCT_HIFN_7811	0x0007		/* 7811 */#define	PCI_PRODUCT_HIFN_7951	0x0012		/* 7951 */#define	PCI_PRODUCT_HIFN_7955	0x0020		/* 7954/7955 */#define	PCI_PRODUCT_HIFN_7956	0x001d		/* 7956 */#define	PCI_VENDOR_INVERTEX	0x14e1		/* Invertex */#define	PCI_PRODUCT_INVERTEX_AEON 0x0005	/* AEON */#define	PCI_VENDOR_NETSEC	0x1660		/* NetSec */#define	PCI_PRODUCT_NETSEC_7751	0x7751		/* 7751 *//* * The values below should multiple of 4 -- and be large enough to handle * any command the driver implements. * * MAX_COMMAND = base command + mac command + encrypt command + *			mac-key + rc4-key * MAX_RESULT  = base result + mac result + mac + encrypt result *			 * */#define	HIFN_MAX_COMMAND	(8 + 8 + 8 + 64 + 260)#define	HIFN_MAX_RESULT		(8 + 4 + 20 + 4)/* * hifn_desc_t * * Holds an individual descriptor for any of the rings. */typedef struct hifn_desc {	volatile u_int32_t l;		/* length and status bits */	volatile u_int32_t p;} hifn_desc_t;/* * Masks for the "length" field of struct hifn_desc. */#define	HIFN_D_LENGTH		0x0000ffff	/* length bit mask */#define	HIFN_D_MASKDONEIRQ	0x02000000	/* mask the done interrupt */#define	HIFN_D_DESTOVER		0x04000000	/* destination overflow */#define	HIFN_D_OVER		0x08000000	/* overflow */#define	HIFN_D_LAST		0x20000000	/* last descriptor in chain */#define	HIFN_D_JUMP		0x40000000	/* jump descriptor */#define	HIFN_D_VALID		0x80000000	/* valid bit *//* * Processing Unit Registers (offset from BASEREG0) */#define	HIFN_0_PUDATA		0x00	/* Processing Unit Data */#define	HIFN_0_PUCTRL		0x04	/* Processing Unit Control */#define	HIFN_0_PUISR		0x08	/* Processing Unit Interrupt Status */#define	HIFN_0_PUCNFG		0x0c	/* Processing Unit Configuration */#define	HIFN_0_PUIER		0x10	/* Processing Unit Interrupt Enable */#define	HIFN_0_PUSTAT		0x14	/* Processing Unit Status/Chip ID */#define	HIFN_0_FIFOSTAT		0x18	/* FIFO Status */#define	HIFN_0_FIFOCNFG		0x1c	/* FIFO Configuration */#define	HIFN_0_SPACESIZE	0x20	/* Register space size *//* Processing Unit Control Register (HIFN_0_PUCTRL) */#define	HIFN_PUCTRL_CLRSRCFIFO	0x0010	/* clear source fifo */#define	HIFN_PUCTRL_STOP	0x0008	/* stop pu */#define	HIFN_PUCTRL_LOCKRAM	0x0004	/* lock ram */#define	HIFN_PUCTRL_DMAENA	0x0002	/* enable dma */#define	HIFN_PUCTRL_RESET	0x0001	/* Reset processing unit *//* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */#define	HIFN_PUISR_CMDINVAL	0x8000	/* Invalid command interrupt */#define	HIFN_PUISR_DATAERR	0x4000	/* Data error interrupt */#define	HIFN_PUISR_SRCFIFO	0x2000	/* Source FIFO ready interrupt */#define	HIFN_PUISR_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */#define	HIFN_PUISR_DSTOVER	0x0200	/* Destination overrun interrupt */#define	HIFN_PUISR_SRCCMD	0x0080	/* Source command interrupt */#define	HIFN_PUISR_SRCCTX	0x0040	/* Source context interrupt */#define	HIFN_PUISR_SRCDATA	0x0020	/* Source data interrupt */#define	HIFN_PUISR_DSTDATA	0x0010	/* Destination data interrupt */#define	HIFN_PUISR_DSTRESULT	0x0004	/* Destination result interrupt *//* Processing Unit Configuration Register (HIFN_0_PUCNFG) */#define	HIFN_PUCNFG_DRAMMASK	0xe000	/* DRAM size mask */#define	HIFN_PUCNFG_DSZ_256K	0x0000	/* 256k dram */#define	HIFN_PUCNFG_DSZ_512K	0x2000	/* 512k dram */#define	HIFN_PUCNFG_DSZ_1M	0x4000	/* 1m dram */#define	HIFN_PUCNFG_DSZ_2M	0x6000	/* 2m dram */#define	HIFN_PUCNFG_DSZ_4M	0x8000	/* 4m dram */#define	HIFN_PUCNFG_DSZ_8M	0xa000	/* 8m dram */#define	HIFN_PUNCFG_DSZ_16M	0xc000	/* 16m dram */#define	HIFN_PUCNFG_DSZ_32M	0xe000	/* 32m dram */#define	HIFN_PUCNFG_DRAMREFRESH	0x1800	/* DRAM refresh rate mask */#define	HIFN_PUCNFG_DRFR_512	0x0000	/* 512 divisor of ECLK */#define	HIFN_PUCNFG_DRFR_256	0x0800	/* 256 divisor of ECLK */#define	HIFN_PUCNFG_DRFR_128	0x1000	/* 128 divisor of ECLK */#define	HIFN_PUCNFG_TCALLPHASES	0x0200	/* your guess is as good as mine... */#define	HIFN_PUCNFG_TCDRVTOTEM	0x0100	/* your guess is as good as mine... */#define	HIFN_PUCNFG_BIGENDIAN	0x0080	/* DMA big endian mode */#define	HIFN_PUCNFG_BUS32	0x0040	/* Bus width 32bits */#define	HIFN_PUCNFG_BUS16	0x0000	/* Bus width 16 bits */#define	HIFN_PUCNFG_CHIPID	0x0020	/* Allow chipid from PUSTAT */#define	HIFN_PUCNFG_DRAM	0x0010	/* Context RAM is DRAM */#define	HIFN_PUCNFG_SRAM	0x0000	/* Context RAM is SRAM */#define	HIFN_PUCNFG_COMPSING	0x0004	/* Enable single compression context */#define	HIFN_PUCNFG_ENCCNFG	0x0002	/* Encryption configuration *//* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */#define	HIFN_PUIER_CMDINVAL	0x8000	/* Invalid command interrupt */#define	HIFN_PUIER_DATAERR	0x4000	/* Data error interrupt */#define	HIFN_PUIER_SRCFIFO	0x2000	/* Source FIFO ready interrupt */#define	HIFN_PUIER_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */#define	HIFN_PUIER_DSTOVER	0x0200	/* Destination overrun interrupt */#define	HIFN_PUIER_SRCCMD	0x0080	/* Source command interrupt */#define	HIFN_PUIER_SRCCTX	0x0040	/* Source context interrupt */#define	HIFN_PUIER_SRCDATA	0x0020	/* Source data interrupt */#define	HIFN_PUIER_DSTDATA	0x0010	/* Destination data interrupt */#define	HIFN_PUIER_DSTRESULT	0x0004	/* Destination result interrupt *//* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */#define	HIFN_PUSTAT_CMDINVAL	0x8000	/* Invalid command interrupt */#define	HIFN_PUSTAT_DATAERR	0x4000	/* Data error interrupt */#define	HIFN_PUSTAT_SRCFIFO	0x2000	/* Source FIFO ready interrupt */#define	HIFN_PUSTAT_DSTFIFO	0x1000	/* Destination FIFO ready interrupt */#define	HIFN_PUSTAT_DSTOVER	0x0200	/* Destination overrun interrupt */#define	HIFN_PUSTAT_SRCCMD	0x0080	/* Source command interrupt */#define	HIFN_PUSTAT_SRCCTX	0x0040	/* Source context interrupt */#define	HIFN_PUSTAT_SRCDATA	0x0020	/* Source data interrupt */#define	HIFN_PUSTAT_DSTDATA	0x0010	/* Destination data interrupt */#define	HIFN_PUSTAT_DSTRESULT	0x0004	/* Destination result interrupt */#define	HIFN_PUSTAT_CHIPREV	0x00ff	/* Chip revision mask */#define	HIFN_PUSTAT_CHIPENA	0xff00	/* Chip enabled mask */#define	HIFN_PUSTAT_ENA_2	0x1100	/* Level 2 enabled */#define	HIFN_PUSTAT_ENA_1	0x1000	/* Level 1 enabled */#define	HIFN_PUSTAT_ENA_0	0x3000	/* Level 0 enabled */#define	HIFN_PUSTAT_REV_2	0x0020	/* 7751 PT6/2 */#define	HIFN_PUSTAT_REV_3	0x0030	/* 7751 PT6/3 *//* FIFO Status Register (HIFN_0_FIFOSTAT) */#define	HIFN_FIFOSTAT_SRC	0x7f00	/* Source FIFO available */#define	HIFN_FIFOSTAT_DST	0x007f	/* Destination FIFO available *//* FIFO Configuration Register (HIFN_0_FIFOCNFG) */#define	HIFN_FIFOCNFG_THRESHOLD	0x0400	/* must be written as 1 *//* * DMA Interface Registers (offset from BASEREG1) */#define	HIFN_1_DMA_CRAR		0x0c	/* DMA Command Ring Address */#define	HIFN_1_DMA_SRAR		0x1c	/* DMA Source Ring Address */#define	HIFN_1_DMA_RRAR		0x2c	/* DMA Result Ring Address */#define	HIFN_1_DMA_DRAR		0x3c	/* DMA Destination Ring Address */#define	HIFN_1_DMA_CSR		0x40	/* DMA Status and Control */#define	HIFN_1_DMA_IER		0x44	/* DMA Interrupt Enable */#define	HIFN_1_DMA_CNFG		0x48	/* DMA Configuration */#define	HIFN_1_PLL		0x4c	/* 7955/7956: PLL config */#define	HIFN_1_7811_RNGENA	0x60	/* 7811: rng enable */#define	HIFN_1_7811_RNGCFG	0x64	/* 7811: rng config */#define	HIFN_1_7811_RNGDAT	0x68	/* 7811: rng data */#define	HIFN_1_7811_RNGSTS	0x6c	/* 7811: rng status */#define	HIFN_1_7811_MIPSRST	0x94	/* 7811: MIPS reset */#define	HIFN_1_REVID		0x98	/* Revision ID */#define	HIFN_1_PUB_RESET	0x204	/* Public/RNG Reset */#define	HIFN_1_PUB_BASE		0x300	/* Public Base Address */#define	HIFN_1_PUB_OPLEN	0x304	/* Public Operand Length */#define	HIFN_1_PUB_OP		0x308	/* Public Operand */#define	HIFN_1_PUB_STATUS	0x30c	/* Public Status */#define	HIFN_1_PUB_IEN		0x310	/* Public Interrupt nable */#define	HIFN_1_RNG_CONFIG	0x314	/* RNG config */#define	HIFN_1_RNG_DATA		0x318	/* RNG data */#define	HIFN_1_PUB_MEM		0x400	/* start of Public key memory */#define	HIFN_1_PUB_MEMEND	0xbff	/* end of Public key memory *//* DMA Status and Control Register (HIFN_1_DMA_CSR) */#define	HIFN_DMACSR_D_CTRLMASK	0xc0000000	/* Destinition Ring Control */#define	HIFN_DMACSR_D_CTRL_NOP	0x00000000	/* Dest. Control: no-op */#define	HIFN_DMACSR_D_CTRL_DIS	0x40000000	/* Dest. Control: disable */#define	HIFN_DMACSR_D_CTRL_ENA	0x80000000	/* Dest. Control: enable */#define	HIFN_DMACSR_D_ABORT	0x20000000	/* Destinition Ring PCIAbort */#define	HIFN_DMACSR_D_DONE	0x10000000	/* Destinition Ring Done */#define	HIFN_DMACSR_D_LAST	0x08000000	/* Destinition Ring Last */#define	HIFN_DMACSR_D_WAIT	0x04000000	/* Destinition Ring Waiting */#define	HIFN_DMACSR_D_OVER	0x02000000	/* Destinition Ring Overflow */