#define	HIFN_DMACSR_R_CTRL	0x00c00000	/* Result Ring Control */#define	HIFN_DMACSR_R_CTRL_NOP	0x00000000	/* Result Control: no-op */#define	HIFN_DMACSR_R_CTRL_DIS	0x00400000	/* Result Control: disable */#define	HIFN_DMACSR_R_CTRL_ENA	0x00800000	/* Result Control: enable */#define	HIFN_DMACSR_R_ABORT	0x00200000	/* Result Ring PCI Abort */#define	HIFN_DMACSR_R_DONE	0x00100000	/* Result Ring Done */#define	HIFN_DMACSR_R_LAST	0x00080000	/* Result Ring Last */#define	HIFN_DMACSR_R_WAIT	0x00040000	/* Result Ring Waiting */#define	HIFN_DMACSR_R_OVER	0x00020000	/* Result Ring Overflow */#define	HIFN_DMACSR_S_CTRL	0x0000c000	/* Source Ring Control */#define	HIFN_DMACSR_S_CTRL_NOP	0x00000000	/* Source Control: no-op */#define	HIFN_DMACSR_S_CTRL_DIS	0x00004000	/* Source Control: disable */#define	HIFN_DMACSR_S_CTRL_ENA	0x00008000	/* Source Control: enable */#define	HIFN_DMACSR_S_ABORT	0x00002000	/* Source Ring PCI Abort */#define	HIFN_DMACSR_S_DONE	0x00001000	/* Source Ring Done */#define	HIFN_DMACSR_S_LAST	0x00000800	/* Source Ring Last */#define	HIFN_DMACSR_S_WAIT	0x00000400	/* Source Ring Waiting */#define	HIFN_DMACSR_ILLW	0x00000200	/* Illegal write (7811 only) */#define	HIFN_DMACSR_ILLR	0x00000100	/* Illegal read (7811 only) */#define	HIFN_DMACSR_C_CTRL	0x000000c0	/* Command Ring Control */#define	HIFN_DMACSR_C_CTRL_NOP	0x00000000	/* Command Control: no-op */#define	HIFN_DMACSR_C_CTRL_DIS	0x00000040	/* Command Control: disable */#define	HIFN_DMACSR_C_CTRL_ENA	0x00000080	/* Command Control: enable */#define	HIFN_DMACSR_C_ABORT	0x00000020	/* Command Ring PCI Abort */#define	HIFN_DMACSR_C_DONE	0x00000010	/* Command Ring Done */#define	HIFN_DMACSR_C_LAST	0x00000008	/* Command Ring Last */#define	HIFN_DMACSR_C_WAIT	0x00000004	/* Command Ring Waiting */#define	HIFN_DMACSR_PUBDONE	0x00000002	/* Public op done (7951 only) */#define	HIFN_DMACSR_ENGINE	0x00000001	/* Command Ring Engine IRQ *//* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */#define	HIFN_DMAIER_D_ABORT	0x20000000	/* Destination Ring PCIAbort */#define	HIFN_DMAIER_D_DONE	0x10000000	/* Destination Ring Done */#define	HIFN_DMAIER_D_LAST	0x08000000	/* Destination Ring Last */#define	HIFN_DMAIER_D_WAIT	0x04000000	/* Destination Ring Waiting */#define	HIFN_DMAIER_D_OVER	0x02000000	/* Destination Ring Overflow */#define	HIFN_DMAIER_R_ABORT	0x00200000	/* Result Ring PCI Abort */#define	HIFN_DMAIER_R_DONE	0x00100000	/* Result Ring Done */#define	HIFN_DMAIER_R_LAST	0x00080000	/* Result Ring Last */#define	HIFN_DMAIER_R_WAIT	0x00040000	/* Result Ring Waiting */#define	HIFN_DMAIER_R_OVER	0x00020000	/* Result Ring Overflow */#define	HIFN_DMAIER_S_ABORT	0x00002000	/* Source Ring PCI Abort */#define	HIFN_DMAIER_S_DONE	0x00001000	/* Source Ring Done */#define	HIFN_DMAIER_S_LAST	0x00000800	/* Source Ring Last */#define	HIFN_DMAIER_S_WAIT	0x00000400	/* Source Ring Waiting */#define	HIFN_DMAIER_ILLW	0x00000200	/* Illegal write (7811 only) */#define	HIFN_DMAIER_ILLR	0x00000100	/* Illegal read (7811 only) */#define	HIFN_DMAIER_C_ABORT	0x00000020	/* Command Ring PCI Abort */#define	HIFN_DMAIER_C_DONE	0x00000010	/* Command Ring Done */#define	HIFN_DMAIER_C_LAST	0x00000008	/* Command Ring Last */#define	HIFN_DMAIER_C_WAIT	0x00000004	/* Command Ring Waiting */#define	HIFN_DMAIER_PUBDONE	0x00000002	/* public op done (7951 only) */#define	HIFN_DMAIER_ENGINE	0x00000001	/* Engine IRQ *//* DMA Configuration Register (HIFN_1_DMA_CNFG) */#define	HIFN_DMACNFG_BIGENDIAN	0x10000000	/* big endian mode */#define	HIFN_DMACNFG_POLLFREQ	0x00ff0000	/* Poll frequency mask */#define	HIFN_DMACNFG_UNLOCK	0x00000800#define	HIFN_DMACNFG_POLLINVAL	0x00000700	/* Invalid Poll Scalar */#define	HIFN_DMACNFG_LAST	0x00000010	/* Host control LAST bit */#define	HIFN_DMACNFG_MODE	0x00000004	/* DMA mode */#define	HIFN_DMACNFG_DMARESET	0x00000002	/* DMA Reset # */#define	HIFN_DMACNFG_MSTRESET	0x00000001	/* Master Reset # *//* 7811 RNG Enable Register (HIFN_1_7811_RNGENA) */#define	HIFN_7811_RNGENA_ENA	0x00000001	/* enable RNG *//* 7811 RNG Config Register (HIFN_1_7811_RNGCFG) */#define	HIFN_7811_RNGCFG_PRE1	0x00000f00	/* first prescalar */#define	HIFN_7811_RNGCFG_OPRE	0x00000080	/* output prescalar */#define	HIFN_7811_RNGCFG_DEFL	0x00000f80	/* 2 words/ 1/100 sec *//* 7811 RNG Status Register (HIFN_1_7811_RNGSTS) */#define	HIFN_7811_RNGSTS_RDY	0x00004000	/* two numbers in FIFO */#define	HIFN_7811_RNGSTS_UFL	0x00001000	/* rng underflow *//* 7811 MIPS Reset Register (HIFN_1_7811_MIPSRST) */#define	HIFN_MIPSRST_BAR2SIZE	0xffff0000	/* sdram size */#define	HIFN_MIPSRST_GPRAMINIT	0x00008000	/* gpram can be accessed */#define	HIFN_MIPSRST_CRAMINIT	0x00004000	/* ctxram can be accessed */#define	HIFN_MIPSRST_LED2	0x00000400	/* external LED2 */#define	HIFN_MIPSRST_LED1	0x00000200	/* external LED1 */#define	HIFN_MIPSRST_LED0	0x00000100	/* external LED0 */#define	HIFN_MIPSRST_MIPSDIS	0x00000004	/* disable MIPS */#define	HIFN_MIPSRST_MIPSRST	0x00000002	/* warm reset MIPS */#define	HIFN_MIPSRST_MIPSCOLD	0x00000001	/* cold reset MIPS *//* Public key reset register (HIFN_1_PUB_RESET) */#define	HIFN_PUBRST_RESET	0x00000001	/* reset public/rng unit *//* Public operation register (HIFN_1_PUB_OP) */#define	HIFN_PUBOP_AOFFSET	0x0000003e	/* A offset */#define	HIFN_PUBOP_BOFFSET	0x00000fc0	/* B offset */#define	HIFN_PUBOP_MOFFSET	0x0003f000	/* M offset */#define	HIFN_PUBOP_OP_MASK	0x003c0000	/* Opcode: */#define	HIFN_PUBOP_OP_NOP	0x00000000	/*  NOP */#define	HIFN_PUBOP_OP_ADD	0x00040000	/*  ADD */#define	HIFN_PUBOP_OP_ADDC	0x00080000	/*  ADD w/carry */#define	HIFN_PUBOP_OP_SUB	0x000c0000	/*  SUB */#define	HIFN_PUBOP_OP_SUBC	0x00100000	/*  SUB w/carry */#define	HIFN_PUBOP_OP_MODADD	0x00140000	/*  Modular ADD */#define	HIFN_PUBOP_OP_MODSUB	0x00180000	/*  Modular SUB */#define	HIFN_PUBOP_OP_INCA	0x001c0000	/*  INC A */#define	HIFN_PUBOP_OP_DECA	0x00200000	/*  DEC A */#define	HIFN_PUBOP_OP_MULT	0x00240000	/*  MULT */#define	HIFN_PUBOP_OP_MODMULT	0x00280000	/*  Modular MULT */#define	HIFN_PUBOP_OP_MODRED	0x002c0000	/*  Modular Red */#define	HIFN_PUBOP_OP_MODEXP	0x00300000	/*  Modular Exp *//* Public operand length register (HIFN_1_PUB_OPLEN) */#define	HIFN_PUBOPLEN_MODLEN	0x0000007f#define	HIFN_PUBOPLEN_EXPLEN	0x0003ff80#define	HIFN_PUBOPLEN_REDLEN	0x003c0000/* Public status register (HIFN_1_PUB_STATUS) */#define	HIFN_PUBSTS_DONE	0x00000001	/* operation done */#define	HIFN_PUBSTS_CARRY	0x00000002	/* carry *//* Public interrupt enable register (HIFN_1_PUB_IEN) */#define	HIFN_PUBIEN_DONE	0x00000001	/* operation done interrupt *//* Random number generator config register (HIFN_1_RNG_CONFIG) */#define	HIFN_RNGCFG_ENA		0x00000001	/* enable rng *//* * Register offsets in register set 1 */#define	HIFN_UNLOCK_SECRET1	0xf4#define	HIFN_UNLOCK_SECRET2	0xfc/* * PLL config register  */#define	HIFN_PLL_7956		0x00001d19	/* 7956 PLL config value */ /********************************************************************* * Structs for board commands  * *********************************************************************//* * Structure to help build up the command data structure. */typedef struct hifn_base_command {	volatile u_int16_t masks;	volatile u_int16_t session_num;	volatile u_int16_t total_source_count;	volatile u_int16_t total_dest_count;} hifn_base_command_t;#define	HIFN_BASE_CMD_MAC		0x0400#define	HIFN_BASE_CMD_CRYPT		0x0800#define	HIFN_BASE_CMD_DECODE		0x2000#define	HIFN_BASE_CMD_SRCLEN_M		0xc000#define	HIFN_BASE_CMD_SRCLEN_S		14#define	HIFN_BASE_CMD_DSTLEN_M		0x3000#define	HIFN_BASE_CMD_DSTLEN_S		12#define	HIFN_BASE_CMD_LENMASK_HI	0x30000#define	HIFN_BASE_CMD_LENMASK_LO	0x0ffff/* * Structure to help build up the command data structure. */typedef struct hifn_crypt_command {	volatile u_int16_t masks;	volatile u_int16_t header_skip;	volatile u_int16_t source_count;	volatile u_int16_t reserved;} hifn_crypt_command_t;#define	HIFN_CRYPT_CMD_ALG_MASK		0x0003		/* algorithm: */#define	HIFN_CRYPT_CMD_ALG_DES		0x0000		/*   DES */#define	HIFN_CRYPT_CMD_ALG_3DES		0x0001		/*   3DES */#define	HIFN_CRYPT_CMD_ALG_RC4		0x0002		/*   RC4 */#define	HIFN_CRYPT_CMD_ALG_AES		0x0003		/*   AES */#define	HIFN_CRYPT_CMD_MODE_MASK	0x0018		/* Encrypt mode: */#define	HIFN_CRYPT_CMD_MODE_ECB		0x0000		/*   ECB */#define	HIFN_CRYPT_CMD_MODE_CBC		0x0008		/*   CBC */#define	HIFN_CRYPT_CMD_MODE_CFB		0x0010		/*   CFB */#define	HIFN_CRYPT_CMD_MODE_OFB		0x0018		/*   OFB */#define	HIFN_CRYPT_CMD_CLR_CTX		0x0040		/* clear context */#define	HIFN_CRYPT_CMD_NEW_KEY		0x0800		/* expect new key */#define	HIFN_CRYPT_CMD_NEW_IV		0x1000		/* expect new iv */#define	HIFN_CRYPT_CMD_SRCLEN_M		0xc000#define	HIFN_CRYPT_CMD_SRCLEN_S		14#define	HIFN_CRYPT_CMD_KSZ_MASK		0x0600		/* AES key size: */#define	HIFN_CRYPT_CMD_KSZ_128		0x0000		/*   128 bit */#define	HIFN_CRYPT_CMD_KSZ_192		0x0200		/*   192 bit */#define	HIFN_CRYPT_CMD_KSZ_256		0x0400		/*   256 bit *//* * Structure to help build up the command data structure. */typedef struct hifn_mac_command {	volatile u_int16_t masks;	volatile u_int16_t header_skip;	volatile u_int16_t source_count;	volatile u_int16_t reserved;} hifn_mac_command_t;#define	HIFN_MAC_CMD_ALG_MASK		0x0001#define	HIFN_MAC_CMD_ALG_SHA1		0x0000#define	HIFN_MAC_CMD_ALG_MD5		0x0001#define	HIFN_MAC_CMD_MODE_MASK		0x000c#define	HIFN_MAC_CMD_MODE_HMAC		0x0000#define	HIFN_MAC_CMD_MODE_SSL_MAC	0x0004#define	HIFN_MAC_CMD_MODE_HASH		0x0008#define	HIFN_MAC_CMD_MODE_FULL		0x0004#define	HIFN_MAC_CMD_TRUNC		0x0010#define	HIFN_MAC_CMD_RESULT		0x0020#define	HIFN_MAC_CMD_APPEND		0x0040#define	HIFN_MAC_CMD_SRCLEN_M		0xc000#define	HIFN_MAC_CMD_SRCLEN_S		14/* * MAC POS IPsec initiates authentication after encryption on encodes * and before decryption on decodes. */#define	HIFN_MAC_CMD_POS_IPSEC		0x0200#define	HIFN_MAC_CMD_NEW_KEY		0x0800/* * The poll frequency and poll scalar defines are unshifted values used * to set fields in the DMA Configuration Register. */#ifndef HIFN_POLL_FREQUENCY#define	HIFN_POLL_FREQUENCY	0x1#endif#ifndef HIFN_POLL_SCALAR#define	HIFN_POLL_SCALAR	0x0#endif#define	HIFN_MAX_SEGLEN 	0xffff		/* maximum dma segment len */#define	HIFN_MAX_DMALEN		0x3ffff		/* maximum dma length */#endif /* __HIFN_H__ */