/*- * Copyright (c) 2003 Sam Leffler, Errno Consulting * Copyright (c) 2003 Global Technology Associates, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD: src/sys/dev/safe/safereg.h,v 1.1 2003/07/21 21:46:07 sam Exp $ */#ifndef _SAFE_SAFEREG_H_#define	_SAFE_SAFEREG_H_/* * Register definitions for SafeNet SafeXcel-1141 crypto device. * Definitions from revision 1.3 (Nov 6 2002) of the User's Manual. */#define BS_BAR			0x10	/* DMA base address register */#define	BS_TRDY_TIMEOUT		0x40	/* TRDY timeout */#define	BS_RETRY_TIMEOUT	0x41	/* DMA retry timeout */#define	PCI_VENDOR_SAFENET	0x16ae		/* SafeNet, Inc. *//* SafeNet */#define	PCI_PRODUCT_SAFEXCEL	0x1141		/* 1141 */#define	SAFE_PE_CSR		0x0000	/* Packet Enginge Ctrl/Status */#define	SAFE_PE_SRC		0x0004	/* Packet Engine Source */#define	SAFE_PE_DST		0x0008	/* Packet Engine Destination */#define	SAFE_PE_SA		0x000c	/* Packet Engine SA */#define	SAFE_PE_LEN		0x0010	/* Packet Engine Length */#define	SAFE_PE_DMACFG		0x0040	/* Packet Engine DMA Configuration */#define	SAFE_PE_DMASTAT		0x0044	/* Packet Engine DMA Status */#define	SAFE_PE_PDRBASE		0x0048	/* Packet Engine Descriptor Ring Base */#define	SAFE_PE_RDRBASE		0x004c	/* Packet Engine Result Ring Base */#define	SAFE_PE_RINGCFG		0x0050	/* Packet Engine Ring Configuration */#define	SAFE_PE_RINGPOLL	0x0054	/* Packet Engine Ring Poll */#define	SAFE_PE_IRNGSTAT	0x0058	/* Packet Engine Internal Ring Status */#define	SAFE_PE_ERNGSTAT	0x005c	/* Packet Engine External Ring Status */#define	SAFE_PE_IOTHRESH	0x0060	/* Packet Engine I/O Threshold */#define	SAFE_PE_GRNGBASE	0x0064	/* Packet Engine Gather Ring Base */#define	SAFE_PE_SRNGBASE	0x0068	/* Packet Engine Scatter Ring Base */#define	SAFE_PE_PARTSIZE	0x006c	/* Packet Engine Particlar Ring Size */#define	SAFE_PE_PARTCFG		0x0070	/* Packet Engine Particle Ring Config */#define	SAFE_CRYPTO_CTRL	0x0080	/* Crypto Control */#define	SAFE_DEVID		0x0084	/* Device ID */#define	SAFE_DEVINFO		0x0088	/* Device Info */#define	SAFE_HU_STAT		0x00a0	/* Host Unmasked Status */#define	SAFE_HM_STAT		0x00a4	/* Host Masked Status (read-only) */#define	SAFE_HI_CLR		0x00a4	/* Host Clear Interrupt (write-only) */#define	SAFE_HI_MASK		0x00a8	/* Host Mask Control */#define	SAFE_HI_CFG		0x00ac	/* Interrupt Configuration */#define	SAFE_HI_RD_DESCR	0x00b4	/* Force Descriptor Read */#define	SAFE_HI_DESC_CNT	0x00b8	/* Host Descriptor Done Count */#define	SAFE_DMA_ENDIAN		0x00c0	/* Master Endian Status */#define	SAFE_DMA_SRCADDR	0x00c4	/* DMA Source Address Status */#define	SAFE_DMA_DSTADDR	0x00c8	/* DMA Destination Address Status */#define	SAFE_DMA_STAT		0x00cc	/* DMA Current Status */#define	SAFE_DMA_CFG		0x00d4	/* DMA Configuration/Status */#define	SAFE_ENDIAN		0x00e0	/* Endian Configuration */#define	SAFE_PK_A_ADDR		0x0800	/* Public Key A Address */#define	SAFE_PK_B_ADDR		0x0804	/* Public Key B Address */#define	SAFE_PK_C_ADDR		0x0808	/* Public Key C Address */#define	SAFE_PK_D_ADDR		0x080c	/* Public Key D Address */#define	SAFE_PK_A_LEN		0x0810	/* Public Key A Length */#define	SAFE_PK_B_LEN		0x0814	/* Public Key B Length */#define	SAFE_PK_SHIFT		0x0818	/* Public Key Shift */#define	SAFE_PK_FUNC		0x081c	/* Public Key Function */#define	SAFE_RNG_OUT		0x0100	/* RNG Output */#define	SAFE_RNG_STAT		0x0104	/* RNG Status */#define	SAFE_RNG_CTRL		0x0108	/* RNG Control */#define	SAFE_RNG_A		0x010c	/* RNG A */#define	SAFE_RNG_B		0x0110	/* RNG B */#define	SAFE_RNG_X_LO		0x0114	/* RNG X [31:0] */#define	SAFE_RNG_X_MID		0x0118	/* RNG X [63:32] */#define	SAFE_RNG_X_HI		0x011c	/* RNG X [80:64] */#define	SAFE_RNG_X_CNTR		0x0120	/* RNG Counter */#define	SAFE_RNG_ALM_CNT	0x0124	/* RNG Alarm Count */#define	SAFE_RNG_CNFG		0x0128	/* RNG Configuration */#define	SAFE_RNG_LFSR1_LO	0x012c	/* RNG LFSR1 [31:0] */#define	SAFE_RNG_LFSR1_HI	0x0130	/* RNG LFSR1 [47:32] */#define	SAFE_RNG_LFSR2_LO	0x0134	/* RNG LFSR1 [31:0] */#define	SAFE_RNG_LFSR2_HI	0x0138	/* RNG LFSR1 [47:32] */#define	SAFE_PE_CSR_READY	0x00000001	/* ready for processing */#define	SAFE_PE_CSR_DONE	0x00000002	/* h/w completed processing */#define	SAFE_PE_CSR_LOADSA	0x00000004	/* load SA digests */#define	SAFE_PE_CSR_HASHFINAL	0x00000010	/* do hash pad & write result */#define	SAFE_PE_CSR_SABUSID	0x000000c0	/* bus id for SA */#define	SAFE_PE_CSR_SAPCI	0x00000040	/* PCI bus id for SA */#define	SAFE_PE_CSR_NXTHDR	0x0000ff00	/* next hdr value for IPsec */#define	SAFE_PE_CSR_FPAD	0x0000ff00	/* fixed pad for basic ops */#define	SAFE_PE_CSR_STATUS	0x00ff0000	/* operation result status */#define	SAFE_PE_CSR_AUTH_FAIL	0x00010000	/* ICV mismatch (inbound) */#define	SAFE_PE_CSR_PAD_FAIL	0x00020000	/* pad verify fail (inbound) */#define	SAFE_PE_CSR_SEQ_FAIL	0x00040000	/* sequence number (inbound) */#define	SAFE_PE_CSR_XERROR	0x00080000	/* extended error follows */#define	SAFE_PE_CSR_XECODE	0x00f00000	/* extended error code */#define	SAFE_PE_CSR_XECODE_S	20#define	SAFE_PE_CSR_XECODE_BADCMD	0	/* invalid command */#define	SAFE_PE_CSR_XECODE_BADALG	1	/* invalid algorithm */#define	SAFE_PE_CSR_XECODE_ALGDIS	2	/* algorithm disabled */#define	SAFE_PE_CSR_XECODE_ZEROLEN	3	/* zero packet length */#define	SAFE_PE_CSR_XECODE_DMAERR	4	/* bus DMA error */#define	SAFE_PE_CSR_XECODE_PIPEABORT	5	/* secondary bus DMA error */#define	SAFE_PE_CSR_XECODE_BADSPI	6	/* IPsec SPI mismatch */#define	SAFE_PE_CSR_XECODE_TIMEOUT	10	/* failsafe timeout */#define	SAFE_PE_CSR_PAD		0xff000000	/* ESP padding control/status */#define	SAFE_PE_CSR_PAD_MIN	0x00000000	/* minimum IPsec padding */#define	SAFE_PE_CSR_PAD_16	0x08000000	/* pad to 16-byte boundary */#define	SAFE_PE_CSR_PAD_32	0x10000000	/* pad to 32-byte boundary */#define	SAFE_PE_CSR_PAD_64	0x20000000	/* pad to 64-byte boundary */#define	SAFE_PE_CSR_PAD_128	0x40000000	/* pad to 128-byte boundary */#define	SAFE_PE_CSR_PAD_256	0x80000000	/* pad to 256-byte boundary *//* * Check the CSR to see if the PE has returned ownership to * the host.  Note that before processing a descriptor this * must be done followed by a check of the SAFE_PE_LEN register * status bits to avoid premature processing of a descriptor * on its way back to the host. */#define	SAFE_PE_CSR_IS_DONE(_csr) \    (((_csr) & (SAFE_PE_CSR_READY | SAFE_PE_CSR_DONE)) == SAFE_PE_CSR_DONE)#define	SAFE_PE_LEN_LENGTH	0x000fffff	/* total length (bytes) */#define	SAFE_PE_LEN_READY	0x00400000	/* ready for processing */#define	SAFE_PE_LEN_DONE	0x00800000	/* h/w completed processing */#define	SAFE_PE_LEN_BYPASS	0xff000000	/* bypass offset (bytes) */#define	SAFE_PE_LEN_BYPASS_S	24#define	SAFE_PE_LEN_IS_DONE(_len) \    (((_len) & (SAFE_PE_LEN_READY | SAFE_PE_LEN_DONE)) == SAFE_PE_LEN_DONE)/* NB: these apply to HU_STAT, HM_STAT, HI_CLR, and HI_MASK */#define	SAFE_INT_PE_CDONE	0x00000002	/* PE context done */#define	SAFE_INT_PE_DDONE	0x00000008	/* PE descriptor done */#define	SAFE_INT_PE_ERROR	0x00000010	/* PE error */#define	SAFE_INT_PE_ODONE	0x00000020	/* PE operation done */#define	SAFE_HI_CFG_PULSE	0x00000001	/* use pulse interrupt */#define	SAFE_HI_CFG_LEVEL	0x00000000	/* use level interrupt */#define	SAFE_HI_CFG_AUTOCLR	0x00000002	/* auto-clear pulse interrupt */#define	SAFE_ENDIAN_PASS	0x000000e4	/* straight pass-thru */#define	SAFE_ENDIAN_SWAB	0x0000001b	/* swap bytes in 32-bit word */#define	SAFE_PE_DMACFG_PERESET	0x00000001	/* reset packet engine */#define	SAFE_PE_DMACFG_PDRRESET	0x00000002	/* reset PDR counters/ptrs */#define	SAFE_PE_DMACFG_SGRESET	0x00000004	/* reset scatter/gather cache */#define	SAFE_PE_DMACFG_FSENA	0x00000008	/* enable failsafe reset */#define	SAFE_PE_DMACFG_PEMODE	0x00000100	/* packet engine mode */#define	SAFE_PE_DMACFG_SAPREC	0x00000200	/* SA precedes packet */#define	SAFE_PE_DMACFG_PKFOLL	0x00000400	/* packet follows descriptor */#define	SAFE_PE_DMACFG_GPRBID	0x00003000	/* gather particle ring busid */#define	SAFE_PE_DMACFG_GPRPCI	0x00001000	/* PCI gather particle ring */#define	SAFE_PE_DMACFG_SPRBID	0x0000c000	/* scatter part. ring busid */#define	SAFE_PE_DMACFG_SPRPCI	0x00004000	/* PCI scatter part. ring */#define	SAFE_PE_DMACFG_ESDESC	0x00010000	/* endian swap descriptors */#define	SAFE_PE_DMACFG_ESSA	0x00020000	/* endian swap SA data */#define	SAFE_PE_DMACFG_ESPACKET	0x00040000	/* endian swap packet data */#define	SAFE_PE_DMACFG_ESPDESC	0x00080000	/* endian swap particle desc. */#define	SAFE_PE_DMACFG_NOPDRUP	0x00100000	/* supp. PDR ownership update */#define	SAFE_PD_EDMACFG_PCIMODE	0x01000000	/* PCI target mode */#define	SAFE_PE_DMASTAT_PEIDONE	0x00000001	/* PE core input done */#define	SAFE_PE_DMASTAT_PEODONE	0x00000002	/* PE core output done */#define	SAFE_PE_DMASTAT_ENCDONE	0x00000004	/* encryption done */#define	SAFE_PE_DMASTAT_IHDONE	0x00000008	/* inner hash done */#define	SAFE_PE_DMASTAT_OHDONE	0x00000010	/* outer hash (HMAC) done */#define	SAFE_PE_DMASTAT_PADFLT	0x00000020	/* crypto pad fault */#define	SAFE_PE_DMASTAT_ICVFLT	0x00000040	/* ICV fault */#define	SAFE_PE_DMASTAT_SPIMIS	0x00000080	/* SPI mismatch */#define	SAFE_PE_DMASTAT_CRYPTO	0x00000100	/* crypto engine timeout */#define	SAFE_PE_DMASTAT_CQACT	0x00000200	/* command queue active */#define	SAFE_PE_DMASTAT_IRACT	0x00000400	/* input request active */#define	SAFE_PE_DMASTAT_ORACT	0x00000800	/* output request active */#define	SAFE_PE_DMASTAT_PEISIZE	0x003ff000	/* PE input size:32-bit words */#define	SAFE_PE_DMASTAT_PEOSIZE	0xffc00000	/* PE out. size:32-bit words */#define	SAFE_PE_RINGCFG_SIZE	0x000003ff	/* ring size (descriptors) */#define	SAFE_PE_RINGCFG_OFFSET	0xffff0000	/* offset btw desc's (dwords) */#define	SAFE_PE_RINGCFG_OFFSET_S	16#define	SAFE_PE_RINGPOLL_POLL	0x00000fff	/* polling frequency/divisor */#define	SAFE_PE_RINGPOLL_RETRY	0x03ff0000	/* polling frequency/divisor */#define	SAFE_PE_RINGPOLL_CONT	0x80000000	/* continuously poll */#define	SAFE_PE_IRNGSTAT_CQAVAIL 0x00000001	/* command queue available */