#define	SAFE_PE_ERNGSTAT_NEXT	0x03ff0000	/* index of next packet desc. */#define	SAFE_PE_ERNGSTAT_NEXT_S	16#define	SAFE_PE_IOTHRESH_INPUT	0x000003ff	/* input threshold (dwords) */#define	SAFE_PE_IOTHRESH_OUTPUT	0x03ff0000	/* output threshold (dwords) */#define	SAFE_PE_PARTCFG_SIZE	0x0000ffff	/* scatter particle size */#define	SAFE_PE_PARTCFG_GBURST	0x00030000	/* gather particle burst */#define	SAFE_PE_PARTCFG_GBURST_2	0x00000000#define	SAFE_PE_PARTCFG_GBURST_4	0x00010000#define	SAFE_PE_PARTCFG_GBURST_8	0x00020000#define	SAFE_PE_PARTCFG_GBURST_16	0x00030000#define	SAFE_PE_PARTCFG_SBURST	0x000c0000	/* scatter particle burst */#define	SAFE_PE_PARTCFG_SBURST_2	0x00000000#define	SAFE_PE_PARTCFG_SBURST_4	0x00040000#define	SAFE_PE_PARTCFG_SBURST_8	0x00080000#define	SAFE_PE_PARTCFG_SBURST_16	0x000c0000#define	SAFE_PE_PARTSIZE_SCAT	0xffff0000	/* scatter particle ring size */#define	SAFE_PE_PARTSIZE_GATH	0x0000ffff	/* gather particle ring size */#define	SAFE_CRYPTO_CTRL_3DES	0x00000001	/* enable 3DES support */#define	SAFE_CRYPTO_CTRL_PKEY	0x00010000	/* enable public key support */#define	SAFE_CRYPTO_CTRL_RNG	0x00020000	/* enable RNG support */#define	SAFE_DEVINFO_REV_MIN	0x0000000f	/* minor rev for chip */#define	SAFE_DEVINFO_REV_MAJ	0x000000f0	/* major rev for chip */#define	SAFE_DEVINFO_REV_MAJ_S	4#define	SAFE_DEVINFO_DES	0x00000100	/* DES/3DES support present */#define	SAFE_DEVINFO_ARC4	0x00000200	/* ARC4 support present */#define	SAFE_DEVINFO_AES	0x00000400	/* AES support present */#define	SAFE_DEVINFO_MD5	0x00001000	/* MD5 support present */#define	SAFE_DEVINFO_SHA1	0x00002000	/* SHA-1 support present */#define	SAFE_DEVINFO_RIPEMD	0x00004000	/* RIPEMD support present */#define	SAFE_DEVINFO_DEFLATE	0x00010000	/* Deflate support present */#define	SAFE_DEVINFO_SARAM	0x00100000	/* on-chip SA RAM present */#define	SAFE_DEVINFO_EMIBUS	0x00200000	/* EMI bus present */#define	SAFE_DEVINFO_PKEY	0x00400000	/* public key support present */#define	SAFE_DEVINFO_RNG	0x00800000	/* RNG present */#define	SAFE_REV(_maj, _min)	(((_maj) << SAFE_DEVINFO_REV_MAJ_S) | (_min))#define	SAFE_REV_MAJ(_chiprev) \	(((_chiprev) & SAFE_DEVINFO_REV_MAJ) >> SAFE_DEVINFO_REV_MAJ_S)#define	SAFE_REV_MIN(_chiprev)	((_chiprev) & SAFE_DEVINFO_REV_MIN)#define	SAFE_PK_FUNC_MULT	0x00000001	/* Multiply function */#define	SAFE_PK_FUNC_SQUARE	0x00000004	/* Square function */#define	SAFE_PK_FUNC_ADD	0x00000010	/* Add function */#define	SAFE_PK_FUNC_SUB	0x00000020	/* Subtract function */#define	SAFE_PK_FUNC_LSHIFT	0x00000040	/* Left-shift function */#define	SAFE_PK_FUNC_RSHIFT	0x00000080	/* Right-shift function */#define	SAFE_PK_FUNC_DIV	0x00000100	/* Divide function */#define	SAFE_PK_FUNC_CMP	0x00000400	/* Compare function */#define	SAFE_PK_FUNC_COPY	0x00000800	/* Copy function */#define	SAFE_PK_FUNC_EXP16	0x00002000	/* Exponentiate (4-bit ACT) */#define	SAFE_PK_FUNC_EXP4	0x00004000	/* Exponentiate (2-bit ACT) */#define	SAFE_RNG_STAT_BUSY	0x00000001	/* busy, data not valid */#define	SAFE_RNG_CTRL_PRE_LFSR	0x00000001	/* enable output pre-LFSR */#define	SAFE_RNG_CTRL_TST_MODE	0x00000002	/* enable test mode */#define	SAFE_RNG_CTRL_TST_RUN	0x00000004	/* start test state machine */#define	SAFE_RNG_CTRL_ENA_RING1	0x00000008	/* test entropy oscillator #1 */#define	SAFE_RNG_CTRL_ENA_RING2	0x00000010	/* test entropy oscillator #2 */#define	SAFE_RNG_CTRL_DIS_ALARM	0x00000020	/* disable RNG alarm reports */#define	SAFE_RNG_CTRL_TST_CLOCK	0x00000040	/* enable test clock */#define	SAFE_RNG_CTRL_SHORTEN	0x00000080	/* shorten state timers */#define	SAFE_RNG_CTRL_TST_ALARM	0x00000100	/* simulate alarm state */#define	SAFE_RNG_CTRL_RST_LFSR	0x00000200	/* reset LFSR *//* * Packet engine descriptor.  Note that d_csr is a copy of the * SAFE_PE_CSR register and all definitions apply, and d_len * is a copy of the SAFE_PE_LEN register and all definitions apply. * d_src and d_len may point directly to contiguous data or to a * list of ``particle descriptors'' when using scatter/gather i/o. */struct safe_desc {	u_int32_t	d_csr;			/* per-packet control/status */	u_int32_t	d_src;			/* source address */	u_int32_t	d_dst;			/* destination address */	u_int32_t	d_sa;			/* SA address */	u_int32_t	d_len;			/* length, bypass, status */};/* * Scatter/Gather particle descriptor. * * NB: scatter descriptors do not specify a size; this is fixed *     by the setting of the SAFE_PE_PARTCFG register. */struct safe_pdesc {	u_int32_t	pd_addr;		/* particle address */#ifdef __BIG_ENDIAN	u_int16_t	pd_flags;		/* control word */	u_int16_t	pd_size;		/* particle size (bytes) */#else	u_int16_t	pd_flags;		/* control word */	u_int16_t	pd_size;		/* particle size (bytes) */#endif};#define	SAFE_PD_READY	0x0001			/* ready for processing */#define	SAFE_PD_DONE	0x0002			/* h/w completed processing *//* * Security Association (SA) Record (Rev 1).  One of these is * required for each operation processed by the packet engine. */struct safe_sarec {	u_int32_t	sa_cmd0;	u_int32_t	sa_cmd1;	u_int32_t	sa_resv0;	u_int32_t	sa_resv1;	u_int32_t	sa_key[8];		/* DES/3DES/AES key */	u_int32_t	sa_indigest[5];		/* inner digest */	u_int32_t	sa_outdigest[5];	/* outer digest */	u_int32_t	sa_spi;			/* SPI */	u_int32_t	sa_seqnum;		/* sequence number */	u_int32_t	sa_seqmask[2];		/* sequence number mask */	u_int32_t	sa_resv2;	u_int32_t	sa_staterec;		/* address of state record */	u_int32_t	sa_resv3[2];	u_int32_t	sa_samgmt0;		/* SA management field 0 */	u_int32_t	sa_samgmt1;		/* SA management field 0 */};#define	SAFE_SA_CMD0_OP		0x00000007	/* operation code */#define	SAFE_SA_CMD0_OP_CRYPT	0x00000000	/* encrypt/decrypt (basic) */#define	SAFE_SA_CMD0_OP_BOTH	0x00000001	/* encrypt-hash/hash-decrypto */#define	SAFE_SA_CMD0_OP_HASH	0x00000003	/* hash (outbound-only) */#define	SAFE_SA_CMD0_OP_ESP	0x00000000	/* ESP in/out (proto) */#define	SAFE_SA_CMD0_OP_AH	0x00000001	/* AH in/out (proto) */#define	SAFE_SA_CMD0_INBOUND	0x00000008	/* inbound operation */#define	SAFE_SA_CMD0_OUTBOUND	0x00000000	/* outbound operation */#define	SAFE_SA_CMD0_GROUP	0x00000030	/* operation group */#define	SAFE_SA_CMD0_BASIC	0x00000000	/* basic operation */#define	SAFE_SA_CMD0_PROTO	0x00000010	/* protocol/packet operation */#define	SAFE_SA_CMD0_BUNDLE	0x00000020	/* bundled operation (resvd) */#define	SAFE_SA_CMD0_PAD	0x000000c0	/* crypto pad method */#define	SAFE_SA_CMD0_PAD_IPSEC	0x00000000	/* IPsec padding */#define	SAFE_SA_CMD0_PAD_PKCS7	0x00000040	/* PKCS#7 padding */#define	SAFE_SA_CMD0_PAD_CONS	0x00000080	/* constant padding */#define	SAFE_SA_CMD0_PAD_ZERO	0x000000c0	/* zero padding */#define	SAFE_SA_CMD0_CRYPT_ALG	0x00000f00	/* symmetric crypto algorithm */#define	SAFE_SA_CMD0_DES	0x00000000	/* DES crypto algorithm */#define	SAFE_SA_CMD0_3DES	0x00000100	/* 3DES crypto algorithm */#define	SAFE_SA_CMD0_AES	0x00000300	/* AES crypto algorithm */#define	SAFE_SA_CMD0_CRYPT_NULL	0x00000f00	/* null crypto algorithm */#define	SAFE_SA_CMD0_HASH_ALG	0x0000f000	/* hash algorithm */#define	SAFE_SA_CMD0_MD5	0x00000000	/* MD5 hash algorithm */#define	SAFE_SA_CMD0_SHA1	0x00001000	/* SHA-1 hash algorithm */#define	SAFE_SA_CMD0_HASH_NULL	0x0000f000	/* null hash algorithm */#define	SAFE_SA_CMD0_HDR_PROC	0x00080000	/* header processing */#define	SAFE_SA_CMD0_IBUSID	0x00300000	/* input bus id */#define	SAFE_SA_CMD0_IPCI	0x00100000	/* PCI input bus id */#define	SAFE_SA_CMD0_OBUSID	0x00c00000	/* output bus id */#define	SAFE_SA_CMD0_OPCI	0x00400000	/* PCI output bus id */#define	SAFE_SA_CMD0_IVLD	0x03000000	/* IV loading */#define	SAFE_SA_CMD0_IVLD_NONE	0x00000000	/* IV no load (reuse) */#define	SAFE_SA_CMD0_IVLD_IBUF	0x01000000	/* IV load from input buffer */#define	SAFE_SA_CMD0_IVLD_STATE	0x02000000	/* IV load from state */#define	SAFE_SA_CMD0_HSLD	0x0c000000	/* hash state loading */#define	SAFE_SA_CMD0_HSLD_SA	0x00000000	/* hash state load from SA */#define	SAFE_SA_CMD0_HSLD_STATE	0x08000000	/* hash state load from state */#define	SAFE_SA_CMD0_HSLD_NONE	0x0c000000	/* hash state no load */#define	SAFE_SA_CMD0_SAVEIV	0x10000000	/* save IV */#define	SAFE_SA_CMD0_SAVEHASH	0x20000000	/* save hash state */#define	SAFE_SA_CMD0_IGATHER	0x40000000	/* input gather */#define	SAFE_SA_CMD0_OSCATTER	0x80000000	/* output scatter */#define	SAFE_SA_CMD1_HDRCOPY	0x00000002	/* copy header to output */#define	SAFE_SA_CMD1_PAYCOPY	0x00000004	/* copy payload to output */#define	SAFE_SA_CMD1_PADCOPY	0x00000008	/* copy pad to output */#define	SAFE_SA_CMD1_IPV4	0x00000000	/* IPv4 protocol */#define	SAFE_SA_CMD1_IPV6	0x00000010	/* IPv6 protocol */#define	SAFE_SA_CMD1_MUTABLE	0x00000020	/* mutable bit processing */#define	SAFE_SA_CMD1_SRBUSID	0x000000c0	/* state record bus id */#define	SAFE_SA_CMD1_SRPCI	0x00000040	/* state record from PCI */#define	SAFE_SA_CMD1_CRMODE	0x00000300	/* crypto mode */#define	SAFE_SA_CMD1_ECB	0x00000000	/* ECB crypto mode */#define	SAFE_SA_CMD1_CBC	0x00000100	/* CBC crypto mode */#define	SAFE_SA_CMD1_OFB	0x00000200	/* OFB crypto mode */#define	SAFE_SA_CMD1_CFB	0x00000300	/* CFB crypto mode */#define	SAFE_SA_CMD1_CRFEEDBACK	0x00000c00	/* crypto feedback mode */#define	SAFE_SA_CMD1_64BIT	0x00000000	/* 64-bit crypto feedback */#define	SAFE_SA_CMD1_8BIT	0x00000400	/* 8-bit crypto feedback */#define	SAFE_SA_CMD1_1BIT	0x00000800	/* 1-bit crypto feedback */#define	SAFE_SA_CMD1_128BIT	0x00000c00	/* 128-bit crypto feedback */#define	SAFE_SA_CMD1_OPTIONS	0x00001000	/* HMAC/options mutable bit */#define	SAFE_SA_CMD1_HMAC	SAFE_SA_CMD1_OPTIONS#define	SAFE_SA_CMD1_SAREV1	0x00008000	/* SA Revision 1 */#define	SAFE_SA_CMD1_OFFSET	0x00ff0000	/* hash/crypto offset(dwords) */#define	SAFE_SA_CMD1_OFFSET_S	16#define	SAFE_SA_CMD1_AESKEYLEN	0x0f000000	/* AES key length */#define	SAFE_SA_CMD1_AES128	0x02000000	/* 128-bit AES key */#define	SAFE_SA_CMD1_AES192	0x03000000	/* 192-bit AES key */#define	SAFE_SA_CMD1_AES256	0x04000000	/* 256-bit AES key *//*  * Security Associate State Record (Rev 1). */struct safe_sastate {	u_int32_t	sa_saved_iv[4];		/* saved IV (DES/3DES/AES) */	u_int32_t	sa_saved_hashbc;	/* saved hash byte count */	u_int32_t	sa_saved_indigest[5];	/* saved inner digest */};#endif /* _SAFE_SAFEREG_H_ */