?? msp430xe42x.h
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#define TXWAKE (0x04) /* TX Wake up mode */
#define STC (0x02) /* SPI: STC enable 0:on / 1:off */
#define TXEPT (0x01) /* TX Buffer empty */
/* UxRCTL */
#define FE (0x80) /* Frame Error */
#define PE (0x40) /* Parity Error */
#define OE (0x20) /* Overrun Error */
#define BRK (0x10) /* Break detected */
#define URXEIE (0x08) /* RX Error interrupt enable */
#define URXWIE (0x04) /* RX Wake up interrupt enable */
#define RXWAKE (0x02) /* RX Wake up detect */
#define RXERR (0x01) /* RX Error Error */
/************************************************************
* USART 0
************************************************************/
#define U0CTL_ (0x0070) /* USART 0 Control */
sfrb U0CTL = U0CTL_;
#define U0TCTL_ (0x0071) /* USART 0 Transmit Control */
sfrb U0TCTL = U0TCTL_;
#define U0RCTL_ (0x0072) /* USART 0 Receive Control */
sfrb U0RCTL = U0RCTL_;
#define U0MCTL_ (0x0073) /* USART 0 Modulation Control */
sfrb U0MCTL = U0MCTL_;
#define U0BR0_ (0x0074) /* USART 0 Baud Rate 0 */
sfrb U0BR0 = U0BR0_;
#define U0BR1_ (0x0075) /* USART 0 Baud Rate 1 */
sfrb U0BR1 = U0BR1_;
#define U0RXBUF_ (0x0076) /* USART 0 Receive Buffer */
const sfrb U0RXBUF = U0RXBUF_;
#define U0TXBUF_ (0x0077) /* USART 0 Transmit Buffer */
sfrb U0TXBUF = U0TXBUF_;
/* Alternate register names */
#define UCTL0 U0CTL /* USART 0 Control */
#define UTCTL0 U0TCTL /* USART 0 Transmit Control */
#define URCTL0 U0RCTL /* USART 0 Receive Control */
#define UMCTL0 U0MCTL /* USART 0 Modulation Control */
#define UBR00 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR10 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL0_ U0CTL_ /* USART 0 Control */
#define UTCTL0_ U0TCTL_ /* USART 0 Transmit Control */
#define URCTL0_ U0RCTL_ /* USART 0 Receive Control */
#define UMCTL0_ U0MCTL_ /* USART 0 Modulation Control */
#define UBR00_ U0BR0_ /* USART 0 Baud Rate 0 */
#define UBR10_ U0BR1_ /* USART 0 Baud Rate 1 */
#define RXBUF0_ U0RXBUF_ /* USART 0 Receive Buffer */
#define TXBUF0_ U0TXBUF_ /* USART 0 Transmit Buffer */
#define UCTL_0 U0CTL /* USART 0 Control */
#define UTCTL_0 U0TCTL /* USART 0 Transmit Control */
#define URCTL_0 U0RCTL /* USART 0 Receive Control */
#define UMCTL_0 U0MCTL /* USART 0 Modulation Control */
#define UBR0_0 U0BR0 /* USART 0 Baud Rate 0 */
#define UBR1_0 U0BR1 /* USART 0 Baud Rate 1 */
#define RXBUF_0 U0RXBUF /* USART 0 Receive Buffer */
#define TXBUF_0 U0TXBUF /* USART 0 Transmit Buffer */
#define UCTL_0_ U0CTL_ /* USART 0 Control */
#define UTCTL_0_ U0TCTL_ /* USART 0 Transmit Control */
#define URCTL_0_ U0RCTL_ /* USART 0 Receive Control */
#define UMCTL_0_ U0MCTL_ /* USART 0 Modulation Control */
#define UBR0_0_ U0BR0_ /* USART 0 Baud Rate 0 */
#define UBR1_0_ U0BR1_ /* USART 0 Baud Rate 1 */
#define RXBUF_0_ U0RXBUF_ /* USART 0 Receive Buffer */
#define TXBUF_0_ U0TXBUF_ /* USART 0 Transmit Buffer */
/************************************************************
* Timer A3
************************************************************/
#define TAIV_ (0x012E) /* Timer A Interrupt Vector Word */
const sfrw TAIV = TAIV_;
#define TACTL_ (0x0160) /* Timer A Control */
sfrw TACTL = TACTL_;
#define TACCTL0_ (0x0162) /* Timer A Capture/Compare Control 0 */
sfrw TACCTL0 = TACCTL0_;
#define TACCTL1_ (0x0164) /* Timer A Capture/Compare Control 1 */
sfrw TACCTL1 = TACCTL1_;
#define TACCTL2_ (0x0166) /* Timer A Capture/Compare Control 2 */
sfrw TACCTL2 = TACCTL2_;
#define TAR_ (0x0170) /* Timer A */
sfrw TAR = TAR_;
#define TACCR0_ (0x0172) /* Timer A Capture/Compare 0 */
sfrw TACCR0 = TACCR0_;
#define TACCR1_ (0x0174) /* Timer A Capture/Compare 1 */
sfrw TACCR1 = TACCR1_;
#define TACCR2_ (0x0176) /* Timer A Capture/Compare 2 */
sfrw TACCR2 = TACCR2_;
/* Alternate register names */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
#define TASSEL2 (0x0400) /* unused */ /* to distinguish from USART SSELx */
#define TASSEL1 (0x0200) /* Timer A clock source select 0 */
#define TASSEL0 (0x0100) /* Timer A clock source select 1 */
#define ID1 (0x0080) /* Timer A clock input devider 1 */
#define ID0 (0x0040) /* Timer A clock input devider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0*0x10) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10) /* Timer A mode control: 2 - Continous up */
#define MC_3 (3*0x10) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0*0x20) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000) /* Capture mode: 1 - both edges */
/*************************************************************
* Flash Memory
*************************************************************/
#define FCTL1_ (0x0128) /* FLASH Control 1 */
sfrw FCTL1 = FCTL1_;
#define FCTL2_ (0x012A) /* FLASH Control 2 */
sfrw FCTL2 = FCTL2_;
#define FCTL3_ (0x012C) /* FLASH Control 3 */
sfrw FCTL3 = FCTL3_;
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Devide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#ifndef FN2
#define FN2 (0x0004)
#endif
#ifndef FN3
#define FN3 (0x0008)
#endif
#ifndef FN4
#define FN4 (0x0010)
#endif
#define FN5 (0x0020)
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
#define BUSY (0x0001) /* Flash busy: 1 */
#define KEYV (0x0002) /* Flash Key violation flag */
#define ACCVIFG (0x0004) /* Flash Access violation flag */
#define WAIT (0x0008) /* Wait flag for segment write */
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020) /* Flash Emergency Exit */
/************************************************************
* HARDWARE MULTIPLIER
************************************************************/
#define MPY_ (0x0130) /* Multiply Unsigned/Operand 1 */
sfrw MPY = MPY_;
#define MPYS_ (0x0132) /* Multiply Signed/Operand 1 */
sfrw MPYS = MPYS_;
#define MAC_ (0x0134) /* Multiply Unsigned and Accumulate/Operand 1 */
sfrw MAC = MAC_;
#define MACS_ (0x0136) /* Multiply Signed and Accumulate/Operand 1 */
sfrw MACS = MACS_;
#define OP2_ (0x0138) /* Operand 2 */
sfrw OP2 = OP2_;
#define RESLO_ (0x013A) /* Result Low Word */
sfrw RESLO = RESLO_;
#define RESHI_ (0x013C) /* Result High Word */
sfrw RESHI = RESHI_;
#define SUMEXT_ (0x013E) /* Sum Extend */
const sfrw SUMEXT = SUMEXT_;
/************************************************************
* SD16 - Sigma Delta 16 Bit
************************************************************/
#define SD16INCTL0_ (0x00B0) /* SD16 Input Control Register Channel 0 */
sfrb SD16INCTL0 = SD16INCTL0_;
#define SD16INCTL1_ (0x00B1) /* SD16 Input Control Register Channel 1 */
sfrb SD16INCTL1 = SD16INCTL1_;
#define SD16INCTL2_ (0x00B2) /* SD16 Input Control Register Channel 2 */
sfrb SD16INCTL2 = SD16INCTL2_;
#define SD16PRE0_ (0x00B8) /* SD16 Preload Register Channel 0 */
sfrb SD16PRE0 = SD16PRE0_;
#define SD16PRE1_ (0x00B9) /* SD16 Preload Register Channel 1 */
sfrb SD16PRE1 = SD16PRE1_;
#define SD16PRE2_ (0x00BA) /* SD16 Preload Register Channel 2 */
sfrb SD16PRE2 = SD16PRE2_;
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