?? msp430xe42x.h
字號:
#define SD16CTL_ (0x0100) /* Sigma Delta ADC 16 Control Register */
sfrw SD16CTL = SD16CTL_;
#define SD16CCTL0_ (0x0102) /* SD16 Channel 0 Control Register */
sfrw SD16CCTL0 = SD16CCTL0_;
#define SD16CCTL1_ (0x0104) /* SD16 Channel 1 Control Register */
sfrw SD16CCTL1 = SD16CCTL1_;
#define SD16CCTL2_ (0x0106) /* SD16 Channel 2 Control Register */
sfrw SD16CCTL2 = SD16CCTL2_;
#define SD16IV_ (0x0110) /* SD16 Interrupt Vector Register */
sfrw SD16IV = SD16IV_;
#define SD16MEM0_ (0x0112) /* SD16 Channel 0 Conversion Memory */
sfrw SD16MEM0 = SD16MEM0_;
#define SD16MEM1_ (0x0114) /* SD16 Channel 1 Conversion Memory */
sfrw SD16MEM1 = SD16MEM1_;
#define SD16MEM2_ (0x0116) /* SD16 Channel 2 Conversion Memory */
sfrw SD16MEM2 = SD16MEM2_;
/* SD16INCTLx - AFEINCTLx */
#define INCH0 (0x0001) /* SD16 Input Channel select 0 */
#define INCH1 (0x0002) /* SD16 Input Channel select 1 */
#define INCH2 (0x0004) /* SD16 Input Channel select 2 */
#define GAIN0 (0x0008) /* AFE Input Pre-Amplifier Gain Select 0 */
#define GAIN1 (0x0010) /* AFE Input Pre-Amplifier Gain Select 1 */
#define GAIN2 (0x0020) /* AFE Input Pre-Amplifier Gain Select 2 */
#define INTDLY0 (0x0040) /* SD16 Interrupt Delay after 1.Conversion 0 */
#define INTDLY1 (0x0080) /* SD16 Interrupt Delay after 1.Conversion 1 */
#define GAIN_1 (0x0000) /* AFE Input Pre-Amplifier Gain Select *1 */
#define GAIN_2 (0x0008) /* AFE Input Pre-Amplifier Gain Select *2 */
#define GAIN_4 (0x0010) /* AFE Input Pre-Amplifier Gain Select *4 */
#define GAIN_8 (0x0018) /* AFE Input Pre-Amplifier Gain Select *8 */
#define GAIN_16 (0x0020) /* AFE Input Pre-Amplifier Gain Select *16 */
#define GAIN_32 (0x0028) /* AFE Input Pre-Amplifier Gain Select *32 */
#define INCH_0 (0x0000) /* SD16 Input Channel select input */
#define INCH_1 (0x0001) /* SD16 Input Channel select input */
#define INCH_2 (0x0002) /* SD16 Input Channel select input */
#define INCH_3 (0x0003) /* SD16 Input Channel select input */
#define INCH_4 (0x0004) /* SD16 Input Channel select input */
#define INCH_5 (0x0005) /* SD16 Input Channel select input */
#define INCH_6 (0x0006) /* SD16 Input Channel select Temp */
#define INCH_7 (0x0007) /* SD16 Input Channel select Offset */
/* SD16CTL - AFECTL */
#define SD16OVIE (0x0002) /* Overflow Interupt Enable */
#define SD16REFON (0x0004) /* Switch internal Reference on */
#define SD16VMIDON (0x0008) /* Switch Vmid Buffer on */
#define SD16SSEL0 (0x0010) /* AFE Clock Source Select 0 */
#define SD16SSEL1 (0x0020) /* AFE Clock Source Select 1 */
#define SD16DIV0 (0x0040) /* AFE Clock Divider Select 0 */
#define SD16DIV1 (0x0080) /* AFE Clock Divider Select 1 */
#define LP (0x0100) /* AFE Low Power Mode Enable */
#define SD16DIV_0 (0x0000) /* AFE Clock Divider Select /1 */
#define SD16DIV_1 (SD16DIV0) /* AFE Clock Divider Select /2 */
#define SD16DIV_2 (SD16DIV1) /* AFE Clock Divider Select /4 */
#define SD16DIV_3 (SD16DIV0+SD16DIV1) /* AFE Clock Divider Select /8 */
#define SD16SSEL_0 (0x0000) /* AFE Clock Source Select MCLK */
#define SD16SSEL_1 (SD16SSEL0) /* AFE Clock Source Select SMCLK */
#define SD16SSEL_2 (SD16SSEL1) /* AFE Clock Source Select ACLK */
#define SD16SSEL_3 (SD16SSEL0+SD16SSEL1) /* AFE Clock Source Select TACLK */
/* SD16CCTLx - AFECCTLx */
#define GRP (0x0001) /* Grouping of Channels: 0:Off/1:On */
#define SC (0x0002) /* Start Conversion */
#define SD16IFG (0x0004) /* SD16 Channel x Interrupt Flag */
#define SD16IE (0x0008) /* SD16 Channel x Interrupt Enable */
#define DF (0x0010) /* SD16 Channel x Data Format: 0:Unipolar/1:Bipolar */
#define SD16OVIFG (0x0020) /* SD16 Channel x Overflow Interrupt Flag */
#define LSBACC (0x0040) /* SD16 Channel x Access LSB of ADC */
#define LSBTOG (0x0080) /* SD16 Channel x Toggle LSB Output of ADC */
#define OSR0 (0x0100) /* AFE Channel x OverSampling Ratio 0 */
#define OSR1 (0x0200) /* AFE Channel x OverSampling Ratio 1 */
#define SNGL (0x0400) /* SD16 Channel x Single Conversion On/Off */
#define OSR_0 (0x0000) /* AFE Channel x OverSampling Ratio 256 */
#define OSR_1 (0x0100) /* AFE Channel x OverSampling Ratio 128 */
#define OSR_2 (0x0200) /* AFE Channel x OverSampling Ratio 64 */
#define OSR_3 (0x0300) /* AFE Channel x OverSampling Ratio 32 */
/************************************************************
* ESP430E
************************************************************/
#define AFEINCTL0 SD16INCTL0 /* AFE Input Control Register Channel 0 */
#define AFEINCTL1 SD16INCTL1 /* AFE Input Control Register Channel 1 */
#define AFEINCTL2 SD16INCTL2 /* AFE Input Control Register Channel 2 */
#define AFECTL SD16CTL /* Analog Front End Control Register */
#define AFECCTL0 SD16CCTL0 /* AFE Channel 0 Control Register */
#define AFECCTL1 SD16CCTL1 /* AFE Channel 1 Control Register */
#define AFECCTL2 SD16CCTL02 /* AFE Channel 2 Control Register */
#define ESPCTL_ (0x0150) /* ESP430 Control Register */
sfrw ESPCTL = ESPCTL_;
#define MBCTL_ (0x0152) /* Mailbox Control Register */
sfrw MBCTL = MBCTL_;
#define MBIN0_ (0x0154) /* Incoming Mailbox 0 Register */
sfrw MBIN0 = MBIN0_;
#define MBIN1_ (0x0156) /* Incoming Mailbox 1 Register */
sfrw MBIN1 = MBIN1_;
#define MBOUT0_ (0x0158) /* Outgoing Mailbox 0 Register */
sfrw MBOUT0 = MBOUT0_;
#define MBOUT1_ (0x015A) /* Outgoing Mailbox 1 Register */
sfrw MBOUT1 = MBOUT1_;
#define RET0_ (0x01C0) /* ESP430 Return Value 0 */
const sfrw RET0 = RET0_;
#define RET1_ (0x01C2) /* ESP430 Return Value 1 */
const sfrw RET1 = RET1_;
#define RET2_ (0x01C4) /* ESP430 Return Value 2 */
const sfrw RET2 = RET2_;
#define RET3_ (0x01C6) /* ESP430 Return Value 3 */
const sfrw RET3 = RET3_;
#define RET4_ (0x01C8) /* ESP430 Return Value 4 */
const sfrw RET4 = RET4_;
#define RET5_ (0x01CA) /* ESP430 Return Value 5 */
const sfrw RET5 = RET5_;
#define RET6_ (0x01CC) /* ESP430 Return Value 6 */
const sfrw RET6 = RET6_;
#define RET7_ (0x01CE) /* ESP430 Return Value 7 */
const sfrw RET7 = RET7_;
#define RET8_ (0x01D0) /* ESP430 Return Value 8 */
const sfrw RET8 = RET8_;
#define RET9_ (0x01D2) /* ESP430 Return Value 9 */
const sfrw RET9 = RET9_;
#define RET10_ (0x01D4) /* ESP430 Return Value 10 */
const sfrw RET10 = RET10_;
#define RET11_ (0x01D6) /* ESP430 Return Value 11 */
const sfrw RET11 = RET11_;
#define RET12_ (0x01D8) /* ESP430 Return Value 12 */
const sfrw RET12 = RET12_;
#define RET13_ (0x01DA) /* ESP430 Return Value 13 */
const sfrw RET13 = RET13_;
#define RET14_ (0x01DC) /* ESP430 Return Value 14 */
const sfrw RET14 = RET14_;
#define RET15_ (0x01DE) /* ESP430 Return Value 15 */
const sfrw RET15 = RET15_;
#define RET16_ (0x01E0) /* ESP430 Return Value 16 */
const sfrw RET16 = RET16_;
#define RET17_ (0x01E2) /* ESP430 Return Value 17 */
const sfrw RET17 = RET17_;
#define RET18_ (0x01E4) /* ESP430 Return Value 18 */
const sfrw RET18 = RET18_;
#define RET19_ (0x01E6) /* ESP430 Return Value 19 */
const sfrw RET19 = RET19_;
#define RET20_ (0x01E8) /* ESP430 Return Value 20 */
const sfrw RET20 = RET20_;
#define RET21_ (0x01EA) /* ESP430 Return Value 21 */
const sfrw RET21 = RET21_;
#define RET22_ (0x01EC) /* ESP430 Return Value 22 */
const sfrw RET22 = RET22_;
#define RET23_ (0x01EE) /* ESP430 Return Value 23 */
const sfrw RET23 = RET23_;
#define RET24_ (0x01F0) /* ESP430 Return Value 24 */
const sfrw RET24 = RET24_;
#define RET25_ (0x01F2) /* ESP430 Return Value 25 */
const sfrw RET25 = RET25_;
#define RET26_ (0x01F4) /* ESP430 Return Value 26 */
const sfrw RET26 = RET26_;
#define RET27_ (0x01F6) /* ESP430 Return Value 27 */
const sfrw RET27 = RET27_;
#define RET28_ (0x01F8) /* ESP430 Return Value 28 */
const sfrw RET28 = RET28_;
#define RET29_ (0x01FA) /* ESP430 Return Value 29 */
const sfrw RET29 = RET29_;
#define RET30_ (0x01FC) /* ESP430 Return Value 30 */
const sfrw RET30 = RET30_;
#define RET31_ (0x01FE) /* ESP430 Return Value 31 */
const sfrw RET31 = RET31_;
#define ESP430_STAT0 RET0 /* STATUS0 of ESP430 */
#define ESP430_STAT1 RET1 /* STATUS1 of ESP430 */
#define WAVEFSV1 RET2 /* Waveform Sample V1 offset corrected*/
#define WAVEFSI1 RET5 /* Waveform Sample I1 offset corrected*/
#define WAVEFSI2 RET6 /* Waveform Sample I2 offset corrected*/
#define ACTENERGY1_LO RET8 /* Active energy I1 Low Word */
#define ACTENERGY1_HI RET9 /* Active energy I1 High Word */
#define ACTENERGY2_LO RET10 /* Active energy I2 Low Word */
#define ACTENERGY2_HI RET11 /* Active energy I2 High Word*/
#define REACTENERGY_LO RET12 /* Reactive energy Low Word */
#define REACTENERGY_HI RET13 /* Reactive energy High Word */
#define APPENERGY_LO RET14 /* Apparent energy Low Word */
#define APPENERGY_HI RET15 /* Apparent energy High Word */
#define ACTENSPER1_LO RET16 /* Active energy I1 for last mains periode Low Word */
#define ACTENSPER1_HI RET17 /* Active energy I1 for last mains periode High Word */
#define ACTENSPER2_LO RET18 /* Active energy I2 for last mains periode Low Word */
#define ACTENSPER2_HI RET19 /* Active energy I2 for last mains periode High Word */
#define POWERFCT RET20 /* Power factor */
#define CAPIND RET21 /* Power factor: neg: inductive pos: cap. (LowByte)*/
#define MAINSPERIOD RET22 /* Mains period */
#define V1RMS RET23 /* Voltage RMS V1 value last second */
#define IRMS_LO RET24 /* Current RMS value last second I1 I2 Low Word */
#define IRMS_HI RET25 /* Current RMS value last second I1 I2 High Word */
#define VPEAK RET26 /* Voltage V1 absolute peak value */
#define IPEAK RET27 /* Current absolute peak value I1 I2 */
#define LINECYCLCNT_LO RET28 /* Line cycle counter Low Word */
#define LINECYCLCNT_HI RET29 /* Line cycle counter High Word */
#define NMBMEAS_LO RET30 /* Number of Measurements for CPU signal Low Word */
#define NMBMEAS_HI RET31 /* Number of Measurements for CPU signal High Word */
/* ESPCTL */
#define ESPEN (0x0001) /* ESP430 Module enable */
#define ESPSUSP (0x0002) /* ESP430 Module suspend */
#define IREQ (0x0004) /* NOT supported by current ESP430 Software */
/* RET0 - Status0 Flags */
#define WFSRDYFG (0x0001) /* New waveform Samples ready Flag */
#define I2GTI1FG (0x0002) /* Current I2 greater then I1 Flag */
#define ILREACHEDFG (0x0004) /* Interrupt level reached Flag */
#define ENRDYFG (0x0008) /* New Energy values ready Flag */
#define ZXLDFG (0x0010) /* Zero Crossing of V1 Flag (leading edge) */
#define ZXTRFG (0x0020) /* Zero Crossing of V1 Flag (trailing edge) */
#define CALRDYFG (0x0040) /* Calibration values ready Flag */
#define TAMPFG (0x0080) /* Tampering Occured Flag */
#define NEGENFG (0x0100) /* Negativ Energy Flag */
#define VDROPFG (0x0200) /* Voltage drop occured Flag */
#define VPEAKFG (0x0400) /* Voltage exceed VPeak level Flag */
#define I1PEAKFG (0x0800) /* Current exceed I1Peak level Flag */
#define I2PEAKFG (0x1000) /* Current exceed I2Peak level Flag */
//#define RESERVED (0x8000) /* Reserved */
//#define RESERVED (0x8000) /* Reserved */
#define ACTIVEFG (0x8000) /* Measurement or Calibration running Flag */
/* MBCTL */
#define IN0IFG (0x0001) /* Incoming Mail 0 Interrupt Flag */
#define IN1IFG (0x0002) /* Incoming Mail 1 Interrupt Flag */
#define OUT0FG (0x0004) /* Outgoing Mail 0 Flag */
#define OUT1FG (0x0008) /* Outgoing Mail 1 Flag */
#define IN0IE (0x0010) /* Incoming Mail 0 Interrupt Enable */
#define IN1IE (0x0020) /* Incoming Mail 1 Interrupt Enable */
#define CLR0OFF (0x0040) /* Switch off automatic clear of IN0IFG */
#define CLR1OFF (0x0080) /* Switch off automatic clear of IN1IFG */
#define OUT0IFG (0x0100) /* Outgoing Mail 0 Interrupt Flag */
#define OUT1IFG (0x0200) /* Outgoing Mail 1 Interrupt Flag */
#define OUT0IE (0x0400) /* Outgoing Mail 0 Interrupt Enable */
#define OUT1IE (0x0800) /* Outgoing Mail 1 Interrupt Enable */
/* Messages to ESP */
#define mRESET (0x0001) /* Restart ESP430 Software */
#define mSET_MODE (0x0003) /* Set Operation Mode for ESP430 Software */
#define mCLR_EVENT (0x0005) /* Clear Flags for ESP430 Software */
#define mINIT (0x0007) /* Initialize ESP430 Software */
#define mTEMP (0x0009) /* Request Temp. Measurement from ESP430 Software */
#define mSWVERSION (0x000B) /* Request software version of ESP430 */
#define mREAD_PARAM (0x000D) /* Request to read the parameter with no. 揚arameter No.?? 快捷鍵說明
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