#define EXTI_CR2_P5IS      ((uint8_t)0x0C) /*!< EXTI Pin 5  external interrupt sensitivity bit Mask */
#define EXTI_CR2_P4IS      ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */

/* CR3 */
#define EXTI_CR3_PBIS      ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */
#define EXTI_CR3_PDIS      ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */
#define EXTI_CR3_PEIS      ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */
#define EXTI_CR3_PFIS      ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */

/* CONF1 */
#define EXTI_CONF1_PBLIS   ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */
#define EXTI_CONF1_PBHIS   ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */
#define EXTI_CONF1_PDLIS   ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */
#define EXTI_CONF1_PDHIS   ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */
#define EXTI_CONF1_PELIS   ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */
#define EXTI_CONF1_PEHIS   ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */
#define EXTI_CONF1_PFLIS   ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */
#define EXTI_CONF1_PFES    ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */

/* CR4 */
#define EXTI_CR4_PGIS      ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */
#define EXTI_CR4_PHIS      ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */

/* CONF2 */
#define EXTI_CONF2_PFHIS   ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */
#define EXTI_CONF2_PGLIS   ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */
#define EXTI_CONF2_PGHIS   ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */
#define EXTI_CONF2_PHLIS   ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */
#define EXTI_CONF2_PHHIS   ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */
#define EXTI_CONF2_PGBS    ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */
#define EXTI_CONF2_PHDS    ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */

/**
  * @}
  */

/*----------------------------------------------------------------------------ok*/

/**
  * @brief FLASH and Data EEPROM
  */
typedef struct FLASH_struct
{
  __IO uint8_t CR1;        /*!< Flash control register 1 */
  __IO uint8_t CR2;        /*!< Flash control register 2 */
  __IO uint8_t PUKR;       /*!< Flash program memory unprotection register */
  __IO uint8_t DUKR;       /*!< Data EEPROM unprotection register */
  __IO uint8_t IAPSR;      /*!< Flash in-application programming status register */
}
FLASH_TypeDef;

/** @addtogroup FLASH_Registers_Reset_Value
  * @{
  */
#define FLASH_CR1_RESET_VALUE    ((uint8_t)0x00)
#define FLASH_CR2_RESET_VALUE    ((uint8_t)0x00)
#define FLASH_PUKR_RESET_VALUE   ((uint8_t)0xAE)
#define FLASH_DUKR_RESET_VALUE   ((uint8_t)0x56)
#define FLASH_IAPSR_RESET_VALUE  ((uint8_t)0x40)


/**
  * @}
  */

/** @addtogroup FLASH_Registers_Bits_Definition
  * @{
  */
#define FLASH_CR1_EEPM           ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */
#define FLASH_CR1_WAITM          ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */
#define FLASH_CR1_IE             ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */
#define FLASH_CR1_FIX            ((uint8_t)0x01) /*!< Fix programming time Mask */

#define FLASH_CR2_OPT            ((uint8_t)0x80) /*!< Enable write access to option bytes*/
#define FLASH_CR2_WPRG           ((uint8_t)0x40) /*!< Word write once Mask */
#define FLASH_CR2_ERASE          ((uint8_t)0x20) /*!< Erase block Mask */
#define FLASH_CR2_FPRG           ((uint8_t)0x10) /*!< Fast programming mode Mask */
#define FLASH_CR2_PRG            ((uint8_t)0x01) /*!< Program block Mask */

#define FLASH_IAPSR_HVOFF        ((uint8_t)0x40) /*!< End of high voltage flag Mask */
#define FLASH_IAPSR_DUL          ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */
#define FLASH_IAPSR_EOP          ((uint8_t)0x04) /*!< End of operation flag Mask */
#define FLASH_IAPSR_PUL          ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */
#define FLASH_IAPSR_WR_PG_DIS    ((uint8_t)0x01) /*!< Write attempted to protected page Mask */

#define FLASH_PUKR_PUK           ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */

#define FLASH_DUKR_DUK           ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */


/**
  * @}
  */

/*----------------------------------------------------------------------------*/

/**
  * @brief Inter-Integrated Circuit (I2C)
  */
typedef struct I2C_struct
{
  __IO uint8_t CR1;    /*!< I2C control register 1 */
  __IO uint8_t CR2;    /*!< I2C control register 2 */
  __IO uint8_t FREQR;  /*!< I2C frequency register */
  __IO uint8_t OARL;   /*!< I2C own address register 1 LSB */
  __IO uint8_t OARH;   /*!< I2C own address register 1 MSB */
  __IO uint8_t OAR2;   /*!< I2C own address register 2 */
  __IO uint8_t DR;     /*!< I2C data register */
  __IO uint8_t SR1;    /*!< I2C status register 1 */
  __IO uint8_t SR2;    /*!< I2C status register 2 */
  __IO uint8_t SR3;    /*!< I2C status register 3 */
  __IO uint8_t ITR;    /*!< I2C interrupt & DMA register */
  __IO uint8_t CCRL;   /*!< I2C clock control register low */
  __IO uint8_t CCRH;   /*!< I2C clock control register high */
  __IO uint8_t TRISER; /*!< I2C maximum rise time register */
  __IO uint8_t PECR;   /*!< I2CPacket Error Checking register */
}
I2C_TypeDef;

/** @addtogroup I2C_Registers_Reset_Value
  * @{
  */
#define I2C_CR1_RESET_VALUE    ((uint8_t)0x00)
#define I2C_CR2_RESET_VALUE    ((uint8_t)0x00)
#define I2C_FREQR_RESET_VALUE  ((uint8_t)0x00)
#define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
#define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
#define I2C_OAR2_RESET_VALUE   ((uint8_t)0x00)
#define I2C_DR_RESET_VALUE     ((uint8_t)0x00)
#define I2C_SR1_RESET_VALUE    ((uint8_t)0x00)
#define I2C_SR2_RESET_VALUE    ((uint8_t)0x00)
#define I2C_SR3_RESET_VALUE    ((uint8_t)0x00)
#define I2C_ITR_RESET_VALUE    ((uint8_t)0x00)
#define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
#define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
#define I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
#define I2C_PECR_RESET_VALUE   ((uint8_t)0x00)

/**
  * @}
  */

/** @addtogroup I2C_Registers_Bits_Definition
  * @{
  */

#define I2C_CR1_NOSTRETCH   ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */
#define I2C_CR1_ENGC        ((uint8_t)0x40) /*!< General Call Enable */
#define I2C_CR1_ENPEC       ((uint8_t)0x20) /*!< PEC Enable */
#define I2C_CR1_ARP         ((uint8_t)0x10) /*!< ARP Enable */
#define I2C_CR1_SMBTYPE     ((uint8_t)0x08) /*!< SMBus type */
#define I2C_CR1_SMBUS       ((uint8_t)0x02) /*!< SMBus mode */
#define I2C_CR1_PE          ((uint8_t)0x01) /*!< Peripheral Enable */

#define I2C_CR2_SWRST       ((uint8_t)0x80) /*!< Software Reset */
#define I2C_CR2_ALERT       ((uint8_t)0x20) /*!< SMBus Alert*/
#define I2C_CR2_PEC         ((uint8_t)0x10) /*!< Packet Error Checking */
#define I2C_CR2_POS         ((uint8_t)0x08) /*!< Acknowledge */
#define I2C_CR2_ACK         ((uint8_t)0x04) /*!< Acknowledge Enable */
#define I2C_CR2_STOP        ((uint8_t)0x02) /*!< Stop Generation */
#define I2C_CR2_START       ((uint8_t)0x01) /*!< Start Generation */

#define I2C_FREQR_FREQ      ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */

#define I2C_OARL_ADD        ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
#define I2C_OARL_ADD0       ((uint8_t)0x01) /*!< Interface Address bit0 */

#define I2C_OARH_ADDMODE    ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */
#define I2C_OARH_ADDCONF    ((uint8_t)0x40) /*!< Address mode configuration */
#define I2C_OARH_ADD        ((uint8_t)0x06) /*!< Interface Address bits [9..8] */

#define I2C_OAR2_ADD2       ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */
#define I2C_OAR2_ENDUAL     ((uint8_t)0x01) /*!< Dual addressing mode enable */

#define I2C_DR_DR           ((uint8_t)0xFF) /*!< Data Register */

#define I2C_SR1_TXE         ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */
#define I2C_SR1_RXNE        ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */
#define I2C_SR1_STOPF       ((uint8_t)0x10) /*!< Stop detection (Slave mode) */
#define I2C_SR1_ADD10       ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */
#define I2C_SR1_BTF         ((uint8_t)0x04) /*!< Byte Transfer Finished */
#define I2C_SR1_ADDR        ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */
#define I2C_SR1_SB          ((uint8_t)0x01) /*!< Start Bit (Master mode) */

#define I2C_SR2_SMBALERT    ((uint8_t)0x80) /*!< SMBus Alert */
#define I2C_SR2_TIMEOUT     ((uint8_t)0x40) /*!< Time out or TLow error */
#define I2C_SR2_WUFH        ((uint8_t)0x20) /*!< Wake-up from Halt */
#define I2C_SR2_PECERR      ((uint8_t)0x10) /*!< PEC error in reception */
#define I2C_SR2_OVR         ((uint8_t)0x08) /*!< Overrun/Underrun */
#define I2C_SR2_AF          ((uint8_t)0x04) /*!< Acknowledge Failure */
#define I2C_SR2_ARLO        ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */
#define I2C_SR2_BERR        ((uint8_t)0x01) /*!< Bus Error */

#define I2C_SR3_DUALF       ((uint8_t)0x80) /*!< Dual flag (Slave mode) */
#define I2C_SR3_SMBHOST     ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */
#define I2C_SR3_SMBDEFAULT  ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */
#define I2C_SR3_GENCALL     ((uint8_t)0x10) /*!< General Call Header (Slave mode) */
#define I2C_SR3_TRA         ((uint8_t)0x04) /*!< Transmitter/Receiver */
#define I2C_SR3_BUSY        ((uint8_t)0x02) /*!< Bus Busy */
#define I2C_SR3_MSL         ((uint8_t)0x01) /*!< Master/Slave */

#define I2C_ITR_LAST        ((uint8_t)0x10) /*!< DMA Last transfer */
#define I2C_ITR_DMAEN       ((uint8_t)0x08) /*!< DMA request Enable */
#define I2C_ITR_ITBUFEN     ((uint8_t)0x04) /*!< Buffer Interrupt Enable */
#define I2C_ITR_ITEVTEN     ((uint8_t)0x02) /*!< Event Interrupt Enable */
#define I2C_ITR_ITERREN     ((uint8_t)0x01) /*!< Error Interrupt Enable */

#define I2C_CCRL_CCR        ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */

#define I2C_CCRH_FS         ((uint8_t)0x80) /*!< Master Mode Selection */
#define I2C_CCRH_DUTY       ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */
#define I2C_CCRH_CCR        ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */

#define I2C_TRISER_TRISE    ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */

#define I2C_PECR_PEC        ((uint8_t)0xFF) /*!< Packet error checking */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/

/**
  * @brief IR digital interface (IRTIM)
  */
typedef struct IRTIM_struct
{
  __IO uint8_t CR; /*!< control register */
}
IRTIM_TypeDef;
/** @addtogroup IRTIM_Registers_Reset_Value
  * @{
  */
#define IRTIM_CR_RESET_VALUE    ((uint8_t)0x00)


/**
* @}
*/

/** @addtogroup IRTIM_Registers_Bits_Definition
  * @{
  */
/* CR*/
#define IRTIM_CR_EN     ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */
#define IRTIM_CR_HSEN   ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */

/**
  * @}
  */

/*----------------------------------------------------------------------------*/

/**
  * @brief Interrupt Controller (ITC)
  */
typedef struct ITC_struct
{
  __IO uint8_t ISPR1; /*!<  Interrupt Software Priority register 1 */
  __IO uint8_t ISPR2; /*!<  Interrupt Software Priority register 2 */
  __IO uint8_t ISPR3; /*!<  Interrupt Software Priority register 3 */
  __IO uint8_t ISPR4; /*!<  Interrupt Software Priority register 4 */
  __IO uint8_t ISPR5; /*!<  Interrupt Software Priority register 5 */
  __IO uint8_t ISPR6; /*!<  Interrupt Software Priority register 6 */
  __IO uint8_t ISPR7; /*!<  Interrupt Software Priority register 7 */
  __IO uint8_t ISPR8; /*!<  Interrupt Software Priority register 8 */
}
ITC_TypeDef;

/** @addtogroup ITC_Registers_Reset_Value
  * @{
  */
#define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */
/**
  * @}
  */

/*----------------------------------------------------------------------------*/

/**
  * @brief Internal Low Speed Watchdog (IWDG)
  */
typedef struct IWDG_struct
{
  __IO uint8_t KR;  /*!<  Low Speed Watchdog Key Register */
  __IO uint8_t PR;  /*!<  Low Speed Watchdog Prescaler Register */
  __IO uint8_t RLR; /*!<  Low Speed Watchdog Reload Register */
}
IWDG_TypeDef;

/** @addtogroup IWDG_Registers_Reset_Value
  * @{
  */
#define IWDG_RLR_RESET_VALUE    ((uint8_t)0xFF)  /*! <Reload Register Default Value */
#define IWDG_PR_RESET_VALUE     ((uint8_t)0x00)  /*! <Prescaler Register Default Value */
/**
  * @}
  */
/*----------------------------------------------------------------------------*/


/**
  * @brief Wait For Event (WFE) peripheral registers.
  */
/** @addtogroup WFE_Registers
  * @{
  */
typedef struct WFE_struct
{
  __IO uint8_t CR1;  /*!<  Wait for event control register 1 */
  __IO uint8_t CR2;  /*!<  Wait for event control register 2 */
  __IO uint8_t CR3;  /*!<  Wait for event control register 3 */
  __IO uint8_t CR4;  /*!<  Wait for event control register 4 */
}
WFE_TypeDef;