/**
  * @}
  */
/** @addtogroup WFE_Registers_Reset_Value
  * @{
  */

#define WFE_CRX_RESET_VALUE ((uint8_t)0x00) /*!< Reset value wait for event control register */
/**
  * @}
  */

/** @addtogroup WFE_Registers_Bits_Definition
  * @{
  */

#define WFE_CR1_EXTI_EV3      ((uint8_t)0x80)  /*!< External interrupt event 3 Mask */
#define WFE_CR1_EXTI_EV2      ((uint8_t)0x40)  /*!< External interrupt event 2 Mask */
#define WFE_CR1_EXTI_EV1      ((uint8_t)0x20)  /*!< External interrupt event 1 Mask */
#define WFE_CR1_EXTI_EV0      ((uint8_t)0x10)  /*!< External interrupt event 0 Mask */
#define WFE_CR1_TIM1_EV1      ((uint8_t)0x08)  /*!< TIM1 event 1 Mask */
#define WFE_CR1_TIM1_EV0      ((uint8_t)0x04)  /*!< TIM1 event 0 Mask */
#define WFE_CR1_TIM2_EV1      ((uint8_t)0x02)  /*!< TIM2 event 1 Mask */
#define WFE_CR1_TIM2_EV0      ((uint8_t)0x01)  /*!< TIM2 event 0 Mask */

#define WFE_CR2_ADC1_COMP_EV  ((uint8_t)0x80)  /*!< ADC / COMP event Mask*/
#define WFE_CR2_EXTI_EVEF     ((uint8_t)0x40)  /*!< External interrupt event on Port E or Port F Mask */
#define WFE_CR2_EXTI_EVDH     ((uint8_t)0x20)  /*!< External interrupt event on Port D or Port H Mask */
#define WFE_CR2_EXTI_EVBG     ((uint8_t)0x10)  /*!< External interrupt event on Port B or Port G Mask */
#define WFE_CR2_EXTI_EV7      ((uint8_t)0x08)  /*!< External interrupt event 7 Mask */
#define WFE_CR2_EXTI_EV6      ((uint8_t)0x04)  /*!< External interrupt event 6 Mask */
#define WFE_CR2_EXTI_EV5      ((uint8_t)0x02)  /*!< External interrupt event 5 Mask */
#define WFE_CR2_EXTI_EV4      ((uint8_t)0x01)  /*!< External interrupt event 4 Mask */

#define WFE_CR3_DMA1CH23_EV   ((uint8_t)0x80)  /*!< DMA1 channel 2 and 3 interrupt event Mask */
#define WFE_CR3_DMA1CH01_EV   ((uint8_t)0x40)  /*!< DMA1 channel 0 and 1 interrupt event Mask */
#define WFE_CR3_USART1_EV     ((uint8_t)0x20)  /*!< USART1 Rx and Tx interrupt event Mask */
#define WFE_CR3_I2C1_EV       ((uint8_t)0x10)  /*!< I2C1 Rx and Tx interrupt event Mask */
#define WFE_CR3_SPI1_EV       ((uint8_t)0x08)  /*!< SPI1 Rx and Tx interrupt event Mask */
#define WFE_CR3_TIM4_EV       ((uint8_t)0x04)  /*!< TIM4 event Mask */
#define WFE_CR3_TIM3_EV1      ((uint8_t)0x02)  /*!< TIM3 event 1 Mask */
#define WFE_CR3_TIM3_EV0      ((uint8_t)0x01)  /*!< TIM3 event 0 Mask */

#define WFE_CR4_AES_EV        ((uint8_t)0x40)  /*!< AES event Mask */
#define WFE_CR4_TIM5_EV1      ((uint8_t)0x20)  /*!< TIM5 event 1 Mask */
#define WFE_CR4_TIM5_EV0      ((uint8_t)0x10)  /*!< TIM5 event 0 Mask */
#define WFE_CR4_USART3_EV     ((uint8_t)0x08)  /*!< USART3 Rx and Tx interrupt event Mask */
#define WFE_CR4_USART2_EV     ((uint8_t)0x04)  /*!< USART2 Rx and Tx interrupt event Mask */
#define WFE_CR4_SPI2_EV       ((uint8_t)0x02)  /*!< SPI2 Rx and Tx interrupt event Mask */
#define WFE_CR4_RTC_CSS_EV    ((uint8_t)0x01)  /*!< RTC or CSS on LSE interrupt event Mask */


/**
  * @}
  */

/*----------------------------------------------------------------------------*/
/**
  * @brief Option Bytes (OPT)
  */
typedef struct OPT_struct
{
  __IO uint8_t ROP;        /*!< Read-out protection*/
  uint8_t  RESERVED1;
  __IO uint8_t UBC;        /*!< User Boot code size*/
  uint8_t  RESERVED2;
  uint8_t  RESERVED3;
  uint8_t  RESERVED4;
  uint8_t  RESERVED5;
  __IO uint8_t PCODESIZE;
  __IO uint8_t WDG;        /*!< Independent and Window watchdog option */
  __IO uint8_t XTSTARTUP;  /*!< HSE and LSE option */
  __IO uint8_t BOR;        /*!< Brownout option */
}
OPT_TypeDef;

/**
  * @}
  */
/*----------------------------------------------------------------------------*/

/**
  * @brief Reset Controller (RST)
  */
typedef struct RST_struct
{
  __IO uint8_t CR;  /*!< Multiplex Reset Pad */
  __IO uint8_t SR;  /*!< Reset status register */

}
RST_TypeDef;
/**
  * @}
  */

/** @addtogroup RST_Registers_Reset_Value
  * @{
  */

#define RST_CR_RESET_VALUE    ((uint8_t)0x00) /*!< Reset pin configuration register  1 reset value */
#define RST_SR_RESET_VALUE    ((uint8_t)0x01) /*!< Reset status register 2 reset value */

/**
  * @}
  */

/** @addtogroup RST_Registers_Bits_Definition
  * @{
  */
#define RST_SR_BORF           ((uint8_t)0x20) /*!< Brownout reset flag mask           */
#define RST_SR_WWDGF          ((uint8_t)0x10) /*!< Window Watchdog reset flag mask */
#define RST_SR_SWIMF          ((uint8_t)0x08) /*!< SWIM reset flag mask            */
#define RST_SR_ILLOPF         ((uint8_t)0x04) /*!< Illegal opcode reset flag mask    */
#define RST_SR_IWDGF          ((uint8_t)0x02) /*!< Independent Watchdog reset flag mask    */
#define RST_SR_PORF           ((uint8_t)0x01) /*!< Power On Reset (POR) flag mask    */

/**
  * @}
  */
/*----------------------------------------------------------------------------*/

/**
  * @brief Power Control (PWR)
  */
typedef struct PWR_struct
{
  __IO uint8_t CSR1;          /*!< PWR control status register 1 */
  __IO uint8_t CSR2;          /*!< PWR control status register 2 */

}
PWR_TypeDef;
/**
  * @}
  */

/** @addtogroup PWR_Registers_Reset_Value
  * @{
  */

#define PWR_CSR1_RESET_VALUE    ((uint8_t)0x00) /*!< Control Status Register 1 reset value */
#define PWR_CSR2_RESET_VALUE    ((uint8_t)0x00) /*!< Control Status Register 2 reset value */

/**
  * @}
  */

/** @addtogroup PWR_Registers_Bits_Definition
  * @{
  */
#define PWR_CSR1_PVDOF          ((uint8_t)0x40) /*!< PVD output flag mask         */
#define PWR_CSR1_PVDIF          ((uint8_t)0x20) /*!< PVD interrupt flag mask */
#define PWR_CSR1_PVDIEN         ((uint8_t)0x10) /*!< PVD interrupt enable mask            */
#define PWR_CSR1_PLS            ((uint8_t)0x0E) /*!< PVD Level thresholds selector mask    */
#define PWR_CSR1_PVDE           ((uint8_t)0x01) /*!< Power Voltage Detector (PVD) enable mask */


#define PWR_CSR2_FWU            ((uint8_t)0x04) /*!< Fast wake up configuration mask */
#define PWR_CSR2_ULP            ((uint8_t)0x02) /*!< Ultra Low power configuration mask  */
#define PWR_CR2_VREFINTF        ((uint8_t)0x01) /*!< Internal reference voltage status flag mask  */
/**
  * @}
  */
/*----------------------------------------------------------------------------*/

/**
  * @brief Routing Interface (RI)
  */
typedef struct RI_struct
{
  uint8_t RESERVED;
  __IO uint8_t ICR1;   /*!< Timer input capture routing register 1 */
  __IO uint8_t ICR2;   /*!< Timer input capture routing register 2 */
  __IO uint8_t IOIR1;  /*!< I/O input register 1 */
  __IO uint8_t IOIR2;  /*!< I/O input register 2 */
  __IO uint8_t IOIR3;  /*!< I/O input register 3 */
  __IO uint8_t IOCMR1; /*!< I/O control mode register 1 */
  __IO uint8_t IOCMR2; /*!< I/O control mode register 2 */
  __IO uint8_t IOCMR3; /*!< I/O control mode register 3 */
  __IO uint8_t IOSR1;  /*!< I/O switch register 1*/
  __IO uint8_t IOSR2;  /*!< I/O switch register 2*/
  __IO uint8_t IOSR3;  /*!< I/O switch register 3*/
  __IO uint8_t IOGCR;  /*!< I/O group control register */
  __IO uint8_t ASCR1;  /*!< Analog Switch Control register 1 */
  __IO uint8_t ASCR2;  /*!< Analog Switch Control register 2 */
  __IO uint8_t RCR;    /*!< Resistor control register  */
  uint8_t RESERVED1[16];
  __IO uint8_t CR;     /*!< Control Register  */
  __IO uint8_t IOMR1;   /*!< IO Mask Register 1 */
  __IO uint8_t IOMR2;   /*!< IO Mask Register 2 */
  __IO uint8_t IOMR3;   /*!< IO Mask Register 3 */
  __IO uint8_t IOMR4;   /*!< IO Mask Register 4*/
  __IO uint8_t IOIR4;  /*!< I/O input register 4 */
  __IO uint8_t IOCMR4; /*!< I/O control mode register 4 */
  __IO uint8_t IOSR4;  /*!< I/O switch register 4 */
}RI_TypeDef;
/**
  * @}
  */

/** @addtogroup RI_Registers_Reset_Value
  * @{
  */

#define RI_ICR1_RESET_VALUE     ((uint8_t)0x00) /*!< Timer input capture routing register 1 reset value */
#define RI_ICR2_RESET_VALUE     ((uint8_t)0x00) /*!< Timer input capture routing register 2 reset value */

#define RI_IOCMR1_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 1 reset value */
#define RI_IOCMR2_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 2 reset value */
#define RI_IOCMR3_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 3 reset value */

#define RI_IOSR1_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 1 reset value */
#define RI_IOSR2_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 2 reset value */
#define RI_IOSR3_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 3 reset value */

#define RI_IOGCR_RESET_VALUE    ((uint8_t)0xFF) /*!< IO group control register reset value */

#define RI_ASCR1_RESET_VALUE    ((uint8_t)0x00) /*!< Analog switch register 1 reset value */
#define RI_ASCR2_RESET_VALUE    ((uint8_t)0x00) /*!< Analog switch register 2 reset value */
#define RI_RCR_RESET_VALUE      ((uint8_t)0x00) /*!< Resistor control register reset value */

#define RI_IOCMR4_RESET_VALUE   ((uint8_t)0x00) /*!< I/O control mode register 4 reset value */
#define RI_IOSR4_RESET_VALUE    ((uint8_t)0x00) /*!< I/O switch register 4 reset value */

/**
  * @}
  */

/** @addtogroup RI_Registers_Bits_Definition
  * @{
  */
#define RI_ICR1_IC2CS          ((uint8_t)0x1F) /*!< TIM1 Input Capture 2 I/O selection mask */

#define RI_ICR2_IC3CS          ((uint8_t)0x1F) /*!< TIM1 Input Capture 3 I/O selection mask */

#define RI_IOIR1_CH1I          ((uint8_t)0x01) /*!< Channel 1 I/O pin input value */
#define RI_IOIR1_CH4I          ((uint8_t)0x02) /*!< Channel 4 I/O pin input value */
#define RI_IOIR1_CH7I          ((uint8_t)0x04) /*!< Channel 7 I/O pin input value */
#define RI_IOIR1_CH10I         ((uint8_t)0x08) /*!< Channel 10 I/O pin input value */
#define RI_IOIR1_CH13I         ((uint8_t)0x10) /*!< Channel 13 I/O pin input value */
#define RI_IOIR1_CH16I         ((uint8_t)0x20) /*!< Channel 16 I/O pin input value */
#define RI_IOIR1_CH19I         ((uint8_t)0x40) /*!< Channel 19 I/O pin input value */
#define RI_IOIR1_CH22I         ((uint8_t)0x80) /*!< Channel 22 I/O pin input value */

#define RI_IOIR2_CH2I          ((uint8_t)0x01) /*!< Channel 2 I/O pin input value */
#define RI_IOIR2_CH5I          ((uint8_t)0x02) /*!< Channel 5 I/O pin input value */
#define RI_IOIR2_CH8I          ((uint8_t)0x04) /*!< Channel 8 I/O pin input value */
#define RI_IOIR2_CH11I         ((uint8_t)0x08) /*!< Channel 11 I/O pin input value */
#define RI_IOIR2_CH14I         ((uint8_t)0x10) /*!< Channel 14 I/O pin input value */
#define RI_IOIR2_CH17I         ((uint8_t)0x20) /*!< Channel 17 I/O pin input value */
#define RI_IOIR2_CH20I         ((uint8_t)0x40) /*!< Channel 20 I/O pin input value */
#define RI_IOIR2_CH23I         ((uint8_t)0x80) /*!< Channel 23 I/O pin input value */

#define RI_IOIR3_CH3I          ((uint8_t)0x01) /*!< Channel 3 I/O pin input value */
#define RI_IOIR3_CH6I          ((uint8_t)0x02) /*!< Channel 6 I/O pin input value */
#define RI_IOIR3_CH9I          ((uint8_t)0x04) /*!< Channel 9 I/O pin input value */
#define RI_IOIR3_CH12I         ((uint8_t)0x08) /*!< Channel 12 I/O pin input value */
#define RI_IOIR3_CH15I         ((uint8_t)0x10) /*!< Channel 15 I/O pin input value */
#define RI_IOIR3_CH18I         ((uint8_t)0x20) /*!< Channel 18 I/O pin input value */
#define RI_IOIR3_CH21I         ((uint8_t)0x40) /*!< Channel 21 I/O pin input value */
#define RI_IOIR3_CH24I         ((uint8_t)0x80) /*!< Channel 24 I/O pin input value */

#define RI_IOCMR1_CH1M          ((uint8_t)0x01) /*!< Channel 1 I/O control mode */
#define RI_IOCMR1_CH4M          ((uint8_t)0x02) /*!< Channel 4 I/O control mode */
#define RI_IOCMR1_CH7M          ((uint8_t)0x04) /*!< Channel 7 I/O control mode */
#define RI_IOCMR1_CH10M         ((uint8_t)0x08) /*!< Channel 10 I/O control mode */
#define RI_IOCMR1_CH13M         ((uint8_t)0x10) /*!< Channel 13 I/O control mode */
#define RI_IOCMR1_CH16M         ((uint8_t)0x20) /*!< Channel 16 I/O control mode */
#define RI_IOCMR1_CH19M         ((uint8_t)0x40) /*!< Channel 19 I/O control mode */
#define RI_IOCMR1_CH22M         ((uint8_t)0x80) /*!< Channel 22 I/O control mode */

#define RI_IOCMR2_CH2M          ((uint8_t)0x01) /*!< Channel 2 I/O control mode */
#define RI_IOCMR2_CH5M          ((uint8_t)0x02) /*!< Channel 5 I/O control mode */
#define RI_IOCMR2_CH8M          ((uint8_t)0x04) /*!< Channel 8 I/O control mode */
#define RI_IOCMR2_CH11M         ((uint8_t)0x08) /*!< Channel 11 I/O control mode */
#define RI_IOCMR2_CH14M         ((uint8_t)0x10) /*!< Channel 14 I/O control mode */
#define RI_IOCMR2_CH17M         ((uint8_t)0x20) /*!< Channel 17 I/O control mode */
#define RI_IOCMR2_CH20M         ((uint8_t)0x40) /*!< Channel 20 I/O control mode */
#define RI_IOCMR2_CH23M         ((uint8_t)0x80) /*!< Channel 23 I/O control mode */

#define RI_IOCMR3_CH3M          ((uint8_t)0x01) /*!< Channel 3 I/O control mode */
#define RI_IOCMR3_CH6M          ((uint8_t)0x02) /*!< Channel 6 I/O control mode */
#define RI_IOCMR3_CH9M          ((uint8_t)0x04) /*!< Channel 9 I/O control mode */
#define RI_IOCMR3_CH12M         ((uint8_t)0x08) /*!< Channel 12 I/O control mode */
#define RI_IOCMR3_CH15M         ((uint8_t)0x10) /*!< Channel 15 I/O control mode */
#define RI_IOCMR3_CH18M         ((uint8_t)0x20) /*!< Channel 18 I/O control mode */
#define RI_IOCMR3_CH21M         ((uint8_t)0x40) /*!< Channel 21 I/O control mode */
#define RI_IOCMR3_CH24M         ((uint8_t)0x80) /*!< Channel 24 I/O control mode */

#define RI_IOSR1_CH1E          ((uint8_t)0x01) /*!< Channel 1 I/O switch control */
#define RI_IOSR1_CH4E          ((uint8_t)0x02) /*!< Channel 4 I/O switch control */
#define RI_IOSR1_CH7E          ((uint8_t)0x04) /*!< Channel 7 I/O switch control */
#define RI_IOSR1_CH10E         ((uint8_t)0x08) /*!< Channel 10 I/O switch control */
#define RI_IOSR1_CH13E         ((uint8_t)0x10) /*!< Channel 13 I/O switch control */
#define RI_IOSR1_CH16E         ((uint8_t)0x20) /*!< Channel 16 I/O switch control */
#define RI_IOSR1_CH19E         ((uint8_t)0x40) /*!< Channel 19 I/O switch control */
#define RI_IOSR1_CH22E         ((uint8_t)0x80) /*!< Channel 22 I/O switch control */

#define RI_IOSR2_CH2E          ((uint8_t)0x01) /*!< Channel 2 I/O switch control */
#define RI_IOSR2_CH5E          ((uint8_t)0x02) /*!< Channel 5 I/O switch control */
#define RI_IOSR2_CH8E          ((uint8_t)0x04) /*!< Channel 8 I/O switch control */
#define RI_IOSR2_CH11E         ((uint8_t)0x08) /*!< Channel 11 I/O switch control */
#define RI_IOSR2_CH14E         ((uint8_t)0x10) /*!< Channel 14 I/O switch control */
#define RI_IOSR2_CH17E         ((uint8_t)0x20) /*!< Channel 17 I/O switch control */
#define RI_IOSR2_CH20E         ((uint8_t)0x40) /*!< Channel 20 I/O switch control */
#define RI_IOSR2_CH23E         ((uint8_t)0x80) /*!< Channel 23 I/O switch control */

#define RI_IOSR3_CH3E          ((uint8_t)0x01) /*!< Channel 3 I/O switch control */
#define RI_IOSR3_CH6E          ((uint8_t)0x02) /*!< Channel 6 I/O switch control */
#define RI_IOSR3_CH9E          ((uint8_t)0x04) /*!< Channel 9 I/O switch control */
#define RI_IOSR3_CH12E         ((uint8_t)0x08) /*!< Channel 12 I/O switch control */
#define RI_IOSR3_CH15E         ((uint8_t)0x10) /*!< Channel 15 I/O switch control */
#defi