static voidmips64_dma_cache_wback_inv_sc(unsigned long addr, unsigned long size){	unsigned long end, a;	if (size >= scache_size) {		blast_scache();		return;	}	a = addr & ~(sc_lsize - 1);	end = (addr + size) & ~(sc_lsize - 1);	while (1) {		flush_scache_line(a);	/* Hit_Writeback_Inv_SD */		if (a == end) break;		a += sc_lsize;	}}static voidmips64_dma_cache_inv_pc(unsigned long addr, unsigned long size){	unsigned long end, a;	unsigned int flags;	if (size >= (unsigned long)dcache_size) {		blast_dcache();	} else {	        __save_and_cli(flags);		a = addr & ~((unsigned long)dc_lsize - 1);		end = (addr + size) & ~((unsigned long)dc_lsize - 1);		while (1) {			invalidate_dcache_line(a); /* Hit_Inv_D */			if (a == end) break;			a += (unsigned long)dc_lsize;		}		__restore_flags(flags);	}	bc_inv(addr, size);}static voidmips64_dma_cache_inv_sc(unsigned long addr, unsigned long size){	unsigned long end, a;	if (size >= scache_size) {		blast_scache();		return;	}	a = addr & ~(sc_lsize - 1);	end = (addr + size) & ~(sc_lsize - 1);	while (1) {		invalidate_scache_line(a); /* Hit_Writeback_Inv_SD */		if (a == end) break;		a += sc_lsize;	}}static voidmips64_dma_cache_wback(unsigned long addr, unsigned long size){	panic("mips64_dma_cache called - should not happen.\n");}/* * While we're protected against bad userland addresses we don't care * very much about what happens in that case.  Usually a segmentation * fault will dump the process later on anyway ... */static void mips64_flush_cache_sigtramp(unsigned long addr){	protected_writeback_dcache_line(addr & ~(dc_lsize - 1));	protected_flush_icache_line(addr & ~(ic_lsize - 1));}static voidmips64_flush_icache_all(void){	if (mips_cpu.cputype == CPU_20KC) {		blast_icache();	}}/* Detect and size the various caches. */static void __init probe_icache(unsigned long config){        unsigned long config1;	unsigned int lsize;        if (!(config & (1 << 31))) {	        /*		 * Not a MIPS64 complainant CPU.		 * Config 1 register not supported, we assume R4k style.		 */	        icache_size = 1 << (12 + ((config >> 9) & 7));		ic_lsize = 16 << ((config >> 5) & 1);		mips_cpu.icache.linesz = ic_lsize;		/*		 * We cannot infer associativity - assume direct map		 * unless probe template indicates otherwise		 */		if(!mips_cpu.icache.ways) mips_cpu.icache.ways = 1;		mips_cpu.icache.sets =			(icache_size / ic_lsize) / mips_cpu.icache.ways;	} else {	       config1 = read_mips32_cp0_config1();	       if ((lsize = ((config1 >> 19) & 7)))		       mips_cpu.icache.linesz = 2 << lsize;	       else		       mips_cpu.icache.linesz = lsize;	       mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7);	       mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7);	       ic_lsize = mips_cpu.icache.linesz;	       icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways *		             ic_lsize;	}	printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",	       icache_size >> 10, ic_lsize, mips_cpu.icache.ways);}static void __init probe_dcache(unsigned long config){        unsigned long config1;	unsigned int lsize;        if (!(config & (1 << 31))) {	        /*		 * Not a MIPS64 complainant CPU.		 * Config 1 register not supported, we assume R4k style.		 */		dcache_size = 1 << (12 + ((config >> 6) & 7));		dc_lsize = 16 << ((config >> 4) & 1);		mips_cpu.dcache.linesz = dc_lsize;		/*		 * We cannot infer associativity - assume direct map		 * unless probe template indicates otherwise		 */		if(!mips_cpu.dcache.ways) mips_cpu.dcache.ways = 1;		mips_cpu.dcache.sets =			(dcache_size / dc_lsize) / mips_cpu.dcache.ways;	} else {	        config1 = read_mips32_cp0_config1();		if ((lsize = ((config1 >> 10) & 7)))		        mips_cpu.dcache.linesz = 2 << lsize;		else		        mips_cpu.dcache.linesz= lsize;		mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7);		mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7);		dc_lsize = mips_cpu.dcache.linesz;		dcache_size =			mips_cpu.dcache.sets * mips_cpu.dcache.ways			* dc_lsize;	}	printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n",	       dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways);}/* If you even _breathe_ on this function, look at the gcc output * and make sure it does not pop things on and off the stack for * the cache sizing loop that executes in KSEG1 space or else * you will crash and burn badly.  You have been warned. */static int __init probe_scache(unsigned long config){	extern unsigned long stext;	unsigned long flags, addr, begin, end, pow2;	int tmp;	if (mips_cpu.scache.flags == MIPS_CACHE_NOT_PRESENT)		return 0;	tmp = ((config >> 17) & 1);	if(tmp)		return 0;	tmp = ((config >> 22) & 3);	switch(tmp) {	case 0:		sc_lsize = 16;		break;	case 1:		sc_lsize = 32;		break;	case 2:		sc_lsize = 64;		break;	case 3:		sc_lsize = 128;		break;	}	begin = (unsigned long) &stext;	begin &= ~((4 * 1024 * 1024) - 1);	end = begin + (4 * 1024 * 1024);	/* This is such a bitch, you'd think they would make it	 * easy to do this.  Away you daemons of stupidity!	 */	__save_and_cli(flags);	/* Fill each size-multiple cache line with a valid tag. */	pow2 = (64 * 1024);	for(addr = begin; addr < end; addr = (begin + pow2)) {		unsigned long *p = (unsigned long *) addr;		__asm__ __volatile__("nop" : : "r" (*p)); /* whee... */		pow2 <<= 1;	}	/* Load first line with zero (therefore invalid) tag. */	set_taglo(0);	set_taghi(0);	__asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */	__asm__ __volatile__("\n\t.set noreorder\n\t"			     "cache 8, (%0)\n\t"			     ".set reorder\n\t" : : "r" (begin));	__asm__ __volatile__("\n\t.set noreorder\n\t"			     "cache 9, (%0)\n\t"			     ".set reorder\n\t" : : "r" (begin));	__asm__ __volatile__("\n\t.set noreorder\n\t"			     "cache 11, (%0)\n\t"			     ".set reorder\n\t" : : "r" (begin));	/* Now search for the wrap around point. */	pow2 = (128 * 1024);	tmp = 0;	for(addr = (begin + (128 * 1024)); addr < (end); addr = (begin + pow2)) {		__asm__ __volatile__("\n\t.set noreorder\n\t"				     "cache 7, (%0)\n\t"				     ".set reorder\n\t" : : "r" (addr));		__asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */		if(!get_taglo())			break;		pow2 <<= 1;	}	__restore_flags(flags);	addr -= begin;	printk("Secondary cache sized at %dK linesize %d bytes.\n",	       (int) (addr >> 10), sc_lsize);	scache_size = addr;	return 1;}static void __init setup_noscache_funcs(void){	_clear_page = (void *)mips64_clear_page_dc;	_copy_page = (void *)mips64_copy_page_dc;	_flush_cache_all = mips64_flush_cache_all_pc;	___flush_cache_all = mips64_flush_cache_all_pc;	_flush_cache_mm = mips64_flush_cache_mm_pc;	_flush_cache_range = mips64_flush_cache_range_pc;	_flush_cache_page = mips64_flush_cache_page_pc;	_flush_page_to_ram = mips64_flush_page_to_ram_pc;	_flush_icache_page = mips64_flush_icache_page;	_dma_cache_wback_inv = mips64_dma_cache_wback_inv_pc;	_dma_cache_wback = mips64_dma_cache_wback;	_dma_cache_inv = mips64_dma_cache_inv_pc;}static void __init setup_scache_funcs(void){        _flush_cache_all = mips64_flush_cache_all_sc;        ___flush_cache_all = mips64_flush_cache_all_sc;	_flush_cache_mm = mips64_flush_cache_mm_sc;	_flush_cache_range = mips64_flush_cache_range_sc;	_flush_cache_page = mips64_flush_cache_page_sc;	_flush_page_to_ram = mips64_flush_page_to_ram_sc;	_clear_page = (void *)mips64_clear_page_sc;	_copy_page = (void *)mips64_copy_page_sc;	_flush_icache_page = mips64_flush_icache_page_s;	_dma_cache_wback_inv = mips64_dma_cache_wback_inv_sc;	_dma_cache_wback = mips64_dma_cache_wback;	_dma_cache_inv = mips64_dma_cache_inv_sc;}typedef int (*probe_func_t)(unsigned long);static inline void __init setup_scache(unsigned int config){	probe_func_t probe_scache_kseg1;	int sc_present = 0;	/* Maybe the cpu knows about a l2 cache? */	probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));	sc_present = probe_scache_kseg1(config);	if (sc_present) {	  	mips_cpu.scache.linesz = sc_lsize;		/*		 * We cannot infer associativity - assume direct map		 * unless probe template indicates otherwise		 */		if(!mips_cpu.scache.ways) mips_cpu.scache.ways = 1;		mips_cpu.scache.sets =		  (scache_size / sc_lsize) / mips_cpu.scache.ways;		setup_scache_funcs();		return;	}	setup_noscache_funcs();}void __init ld_mmu_mips64(void){	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);	change_cp0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);	probe_icache(config);	probe_dcache(config);	setup_scache(config);	_flush_cache_sigtramp = mips64_flush_cache_sigtramp;	_flush_icache_range = mips64_flush_icache_range;	/* Ouch */	_flush_icache_all = mips64_flush_icache_all;	_flush_cache_l1 = _flush_cache_all;	_flush_cache_l2 = _flush_cache_all;	__flush_cache_all();}