/* universe.c - Tundra Universe chip VME-to-PCI bridge interface library *//* Copyright 1984-1998 Wind River Systems, Inc. *//* Copyright 1996,1997,1998 Motorola, Inc. All Rights Reserved *//*modification history--------------------01w,26mar02,dtr  Removing compiler warnings.01v,24aug98,rhk  fix potential RORA VME interrupt problem01u,07aug98,tb   Fixed PReP VMEbus RMW bug01t,07aug98,tb   Added VMEbus DMA support01s,07aug98,tb   Fixed support for SM_OFF_BOARD01r,15apr98,ms_  collapsed identical macros of VSI[0123]_CTL into one01q,13apr98,mas  restored full 8-bit VME vector reception (SPR 20522).01p,14apr98,ms_  merged Motorola mv2700 support01o,11feb98,tb   Added TAS which uses VMEbus RMW01n,17dec97,tb   Added Universe II support01m,05nov97,mas  VME bus error clearing done by sysUnivVERRClr, no ISR or hook		 (SPR 9717).01l,31oct97,mas  removed int handler loop; fixed sysBusIntGen(); added default		 VME Error handler sysUnivVERRIntr() and _func_sysUnivVERRIntr		 hook (SPR 9438).01k,14aug97,mas  no slave VME A24 space (for cumulative patch release 9/97).01j,09jul97,mas  added interrupt level setting via sysUnivIntLevelSet() (SPR		 8896); added support for UNIVERSE_VOWN_INT; all I/O now done 		 with macros; no #if FALSE and #ifndef DOC dependency in 		 sysUniverseInit().01i,10jun97,wlf  doc: cleanup.01h,24apr97,mas  added support for MPIC (SPR 8170).01g,22apr97,mas  added sysUniverseReset() (SPR 8226).01f,18feb97,mas  added MR #39 to sysUnivVmeIntr; added customer suggestions		 (SPR 7811).01e,07jan97,dat  chgd sysUniverseIntConnect (from Motorola)01d,02jan97,dat  documentation, chgd vme2PciIntr to sysUnivVmeIntr01c,30dec96,wlf  doc: cleanup.01b,18dec96,tb   [Motorola] fixed interrupt disabling/handling (SPR 7525).01a,10jul96,rhk  [Motorola] written.*//*DESCRIPTIONThe routines addressed here include:Initialization of Universe chipBus interrupt functions:.IP "-"enable/disable VMEbus interrupt levels.IP "-"enable/disable additional VME interrupts.IP "-"install handlers for the additional VME interrupts.IP "-"generate bus interruptsMailbox/locations monitor functions:.IP "-"- enable mailbox/location monitor interruptsAll byte I/O is done via the macros UNIV_IN_BYTE and UNIV_OUT_BYTE which may beredefined by the BSP.  By default, sysInByte() and sysOutByte() are used.  Allother I/O (32-bit) is handled by the macros UNIV_IN_LONG and UNIV_OUT_LONGwhich may be redefined by the BSP.  By default, sysPciRead32() andsysPciWrite32() are used.*//* includes */#include "vxWorks.h"#include "config.h"#include "vxLib.h"#ifdef INCLUDE_MPIC#  include "ravenMpic.h"#else#  include "sl82565IntrCtl.h"#endif /* INCLUDE_MPIC */#include "universe.h"/* defines */#ifndef UNIV_IN_BYTE# define UNIV_IN_BYTE(adr,pVal) \  *(volatile UCHAR *)(pVal)=sysInByte((volatile ULONG)(adr))#endif#ifndef UNIV_OUT_BYTE# define UNIV_OUT_BYTE(adr,val) \  sysOutByte((volatile ULONG)(adr),(volatile UCHAR)(val))#endif#ifndef UNIV_IN_LONG# define UNIV_IN_LONG(adr,pVal) \  sysPciRead32((UINT32)(adr),(UINT32 *)(pVal));#endif#ifndef UNIV_OUT_LONG# define UNIV_OUT_LONG(adr,val) \  sysPciWrite32((UINT32)(adr),(UINT32)(val));#endif# ifndef CPU_INT_LOCK#   define CPU_INT_LOCK(pData) (*pData = intLock ())# endif# ifndef CPU_INT_UNLOCK#   define CPU_INT_UNLOCK(data) (intUnlock (data))# endif/* forward declarations */LOCAL FUNCPTR sysMailboxRoutine  = NULL;LOCAL int sysMailboxArg          = 0;#ifdef  INCLUDE_VME_DMALOCAL STATUS sysVmeDmaCopy(UCHAR *, UCHAR *, UINT32, UINT32);#endif /* INCLUDE_VME_DMA *//* extern declarations */IMPORT int    intEnable (int);IMPORT int    intDisable (int);IMPORT void   sysOutByte (ULONG, UCHAR);IMPORT UCHAR  sysInByte (ULONG);IMPORT void   sysPciRead32  (UINT32, UINT32 *);IMPORT void   sysPciWrite32 (UINT32, UINT32);IMPORT void   sysUsDelay (UINT32);IMPORT INT_HANDLER_DESC * sysIntTbl [256];/* globals */int    sysUnivIntsEnabled = 0;	/* currently enabled Universe interrupts */int    sysUnivIntLevel    = 0;	/* current level at which ints are disabled */UINT32 sysUnivVERRCnt     = 0;	/* #VME errors since power on *//* * Universe interrupt priority mapping table  * * Interrupt priority level is equal to the index into the following array * where 0 is the lowest priority.  The prioritization scheme used here * is arbitrary.  If the scheme is changed, the interrupt masks (last column) * must be redefined accordingly.  See universe.h and the Universe Manual for * bit assignments and further information. */static INT_LEVEL_MAP univIntTable[UNIV_NUM_INT + 1] =  {  /* Int Bit Mask	       Int Vector		 Int Level Mask */  /* ------------------------  ------------------------  -------------- */    {0,                        0,                         0x0000F7FF},    {UNIVERSE_VOWN_INT,        UNIV_VOWN_INT_VEC,         0x0000F7FE},    {LVL1,                     -1,                        0x0000F7FC},    {LVL2,                     -1,                        0x0000F7F8},    {LVL3,                     -1,                        0x0000F7F0},    {LVL4,                     -1,                        0x0000F7E0},    {LVL5,                     -1,                        0x0000F7C0},    {LVL6,                     -1,                        0x0000F780},    {LVL7,                     -1,                        0x0000F700},    {UNIVERSE_DMA_INT,         UNIV_DMA_INT_VEC,          0x0000F600},    {UNIVERSE_VME_SW_IACK_INT, UNIV_VME_SW_IACK_INT_VEC,  0x0000E600},    {UNIVERSE_PCI_SW_INT,      UNIV_PCI_SW_INT_VEC,       0x0000C600},    {UNIVERSE_LERR_INT,        UNIV_LERR_INT_VEC,         0x0000C400},    {UNIVERSE_VERR_INT,        UNIV_VERR_INT_VEC,         0x0000C000},    {UNIVERSE_SYSFAIL_INT,     UNIV_SYSFAIL_INT_VEC,      0x00008000},    {UNIVERSE_ACFAIL_INT,      UNIV_ACFAIL_INT_VEC,       0x00000000}  };/* locals */#ifdef  INCLUDE_VME_DMALOCAL BOOL  sysVmeDmaReady = FALSE;#endif /* INCLUDE_VME_DMA *//********************************************************************************* sysUniverseReset - reset the Universe VME chip** This routine performs the reseting of the Universe chip.  All functions* and VME mapping are disabled.** RETURNS: N/A*/void sysUniverseReset (void)    {    UINT32  reg;    /* initialize registers with defaults and disable mapping */    UNIV_OUT_LONG(UNIVERSE_SCYC_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_SCYC_ADDR, 0);    UNIV_OUT_LONG(UNIVERSE_SCYC_EN,   0);    UNIV_OUT_LONG(UNIVERSE_LMISC,     LMISC_CRT_128_USEC);    UNIV_OUT_LONG(UNIVERSE_DCTL,      0);    UNIV_OUT_LONG(UNIVERSE_DTBC,      0);    UNIV_OUT_LONG(UNIVERSE_DLA,       0);    UNIV_OUT_LONG(UNIVERSE_DVA,       0);    UNIV_OUT_LONG(UNIVERSE_DCPP,      0);    UNIV_OUT_LONG(UNIVERSE_LINT_EN,   0);    UNIV_OUT_LONG(UNIVERSE_LINT_MAP0, 0);    UNIV_OUT_LONG(UNIVERSE_LINT_MAP1, 0);    UNIV_OUT_LONG(UNIVERSE_VINT_EN,   0);    UNIV_OUT_LONG(UNIVERSE_VINT_MAP0, 0);    UNIV_OUT_LONG(UNIVERSE_VINT_MAP1, 0);    UNIV_OUT_LONG(UNIVERSE_VSI0_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_VSI1_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_VSI2_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_VSI3_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_LSI0_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_LSI1_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_LSI2_CTL,  0);    UNIV_OUT_LONG(UNIVERSE_LSI3_CTL,  0);    /* clear the SYSFAIL signal */    UNIV_OUT_LONG(UNIVERSE_VCSR_CLR,  VCSR_CLR_SYSFAIL);    /* clear any outstanding interrupts/error conditions */    UNIV_OUT_LONG(UNIVERSE_LINT_STAT, LINT_STAT_CLEAR);    UNIV_OUT_LONG(UNIVERSE_VINT_STAT, VINT_STAT_CLEAR);    UNIV_OUT_LONG(UNIVERSE_V_AMERR, V_AMERR_V_STAT);    UNIV_IN_LONG(UNIVERSE_PCI_CSR, &reg);    reg |= PCI_CSR_D_PE | PCI_CSR_S_SERR | PCI_CSR_R_MA |           PCI_CSR_R_TA | PCI_CSR_S_TA;    UNIV_OUT_LONG(UNIVERSE_PCI_CSR, reg);    UNIV_OUT_LONG(UNIVERSE_L_CMDERR, L_CMDERR_L_ENABLE);    UNIV_OUT_LONG(UNIVERSE_DGCS, DGCS_STOP | DGCS_HALT | DGCS_DONE |                  DGCS_LERR | DGCS_VERR | DGCS_P_ERR);    /* clear and disable the mailbox interrupts */    UNIV_OUT_BYTE(CPU_SIG_LM_CONTROL_REG, (SIG1_INTR_CLEAR |                                           SIG0_INTR_CLEAR |                                           LM1_INTR_CLEAR  |                                           LM0_INTR_CLEAR  ));    UNIV_OUT_BYTE(CPU_SIG_LM_STATUS_REG, ~(SIG1_INTR_ENABL |                                           SIG0_INTR_ENABL |                                           LM1_INTR_ENABL  |                                           LM0_INTR_ENABL  ));    sysUnivIntsEnabled = 0;    sysUnivIntLevel    = 0;    }/********************************************************************************* sysUniverseInit - initialize registers of the Universe chip** This routine initializes registers of the Universe VME-to-PCI bridge and maps* access to the VMEbus memory space.** NOTE: The sysProcNumSet() routine maps the master node's local memory on the* VMEbus.** RETURNS: OK, always.*/STATUS sysUniverseInit (void)    {    UINT32	temp_data;    /* Put vme chip into a power-up/reset state */    sysUniverseReset ();    if (pciToVmeDev == UNIVERSE_I)	{        UNIV_OUT_LONG(UNIVERSE_MAST_CTL, (MAST_CTL_RTRY_FOREVER |                                          MAST_CTL_PWON_4096    |                                          MAST_CTL_VRL3         |                                          MAST_CTL_VRM_DEMAND   |                                          MAST_CTL_VREL_RWD     |                                          MAST_CTL_PABS_32      ));	}    else	{	/* pciToVmeDev == UNIVERSE_II */        UNIV_OUT_LONG(UNIVERSE_MAST_CTL, (MAST_CTL_RTRY_FOREVER |                                          MAST_CTL_PWON_4096    |                                          MAST_CTL_VRL3         |                                          MAST_CTL_VRM_FAIR     |                                          MAST_CTL_VREL_ROR     |                                          MAST_CTL_PABS_128     ));	}    UNIV_IN_LONG(UNIVERSE_MISC_CTL, &temp_data);    /* maintain power-up option bits */    temp_data &= ( MISC_CTL_SYSCON | MISC_CTL_V64AUTO );    temp_data |= ( MISC_CTL_VBTO_256USEC   |		   MISC_CTL_VARB_RROBIN    |		   MISC_CTL_VARBTO_256USEC |		   MISC_CTL_RESCIND        );    UNIV_OUT_LONG(UNIVERSE_MISC_CTL, temp_data);    UNIV_OUT_LONG(UNIVERSE_USER_AM,  0);    UNIV_OUT_LONG(UNIVERSE_VRAI_CTL, 0);    UNIV_OUT_LONG(UNIVERSE_VCSR_CTL, 0);    /* clear the SYSFAIL signal */    UNIV_OUT_LONG(UNIVERSE_VCSR_CLR, VCSR_CLR_SYSFAIL);    /* set the latency timer to max value */    UNIV_OUT_LONG(UNIVERSE_PCI_MISC0, PCI_MISC0_LATENCY_TIMER);    /* Map to get to VMEbus  using A32 */    UNIV_OUT_LONG(UNIVERSE_LSI1_BS,  VAL_LSI1_BS);    UNIV_OUT_LONG(UNIVERSE_LSI1_BD,  VAL_LSI1_BD);    UNIV_OUT_LONG(UNIVERSE_LSI1_TO,  VAL_LSI1_TO);    UNIV_OUT_LONG(UNIVERSE_LSI1_CTL, VAL_LSI1_CTL);    /* Map to get to VMEbus  using A24 */    UNIV_OUT_LONG(UNIVERSE_LSI2_BS,  VAL_LSI2_BS);    UNIV_OUT_LONG(UNIVERSE_LSI2_BD,  VAL_LSI2_BD);    UNIV_OUT_LONG(UNIVERSE_LSI2_TO,  VAL_LSI2_TO);    UNIV_OUT_LONG(UNIVERSE_LSI2_CTL, VAL_LSI2_CTL);    /* Map to get to VMEbus using A16 */    UNIV_OUT_LONG(UNIVERSE_LSI3_BS,  VAL_LSI3_BS);    UNIV_OUT_LONG(UNIVERSE_LSI3_BD,  VAL_LSI3_BD);    UNIV_OUT_LONG(UNIVERSE_LSI3_TO,  VAL_LSI3_TO);    UNIV_OUT_LONG(UNIVERSE_LSI3_CTL, VAL_LSI3_CTL);    /* Map to get to VMEbus LM/SIG Registers using A32 */    UNIV_OUT_LONG(UNIVERSE_LSI0_BS,  VAL_LSI0_BS);    UNIV_OUT_LONG(UNIVERSE_LSI0_BD,  VAL_LSI0_BD);    UNIV_OUT_LONG(UNIVERSE_LSI0_TO,  VAL_LSI0_TO);    UNIV_OUT_LONG(UNIVERSE_LSI0_CTL, VAL_LSI0_CTL);    return (OK);    }/********************************************************************************* sysUniverseInit2 - enable local memory accesses from the VMEbus** This routine enables local resources to be accessed from the VMEbus.* All target boards have an A32 window opened to access the VMEbus LM/SIG* registers.  However, only the master node has an A32 and an A24* window open to its local memory space.** RETURNS: N/A** NOMANUAL*/void sysUniverseInit2    (    int         procNum                 /* processor number */    )    {#ifndef DOC    /* setup the VME LM/SIG/SEM registers address range */    UNIV_OUT_LONG(UNIVERSE_VSI0_BS,  VAL_VSI0_BS);    UNIV_OUT_LONG(UNIVERSE_VSI0_BD,  VAL_VSI0_BD);    UNIV_OUT_LONG(UNIVERSE_VSI0_TO,  VAL_VSI0_TO);    if (pciToVmeDev == UNIVERSE_I)	{        UNIV_OUT_LONG(UNIVERSE_VSI0_CTL, VAL_VSI0_CTL);	}    else	{	/* pciToVmeDev == UNIVERSE_II */        UNIV_OUT_LONG(UNIVERSE_VSI0_CTL, VAL_VSI0_CTL | VSI_CTL_PWEN);	}    if (procNum == 0)        {        /* setup the A32 window */        UNIV_OUT_LONG(UNIVERSE_VSI1_BS,  VAL_VSI1_BS);        UNIV_OUT_LONG(UNIVERSE_VSI1_BD,  VAL_VSI1_BD);        UNIV_OUT_LONG(UNIVERSE_VSI1_TO,  VAL_VSI1_TO);	if (pciToVmeDev == UNIVERSE_I)	    {            UNIV_OUT_LONG(UNIVERSE_VSI1_CTL, VAL_VSI1_CTL);	    }        else	    {	    /* pciToVmeDev == UNIVERSE_II */	    UNIV_OUT_LONG(UNIVERSE_VSI1_CTL, VAL_VSI1_CTL | VSI_CTL_PWEN);#if	(SM_OFF_BOARD == FALSE)#ifndef	ANY_BRDS_IN_CHASSIS_NOT_RMW            /*	     * All slave boards in the chassis generate a VMEbus RMW, and	     * the master is capable of translating an incoming RMW into	     * an atomic operation.	     */	    /*	     * The A32 access range is now divided into 3 separate windows.	     * The first window will allow normal access to the start of local	     * memory up to the Shared Memory Region.  It is defined above	     * thru the use of a conditional #define VAL_VSI1_BD in mv2600.h.	     * The second window will allow Read-Modify-Write (RMW) access to	     * the Standard VxWorks and VxMP's Shared Memory Region.  The	     * third window will allow normal access to the local memory	     * starting after the Shared Memory Region up to the end of	     * physical memory.	     */            /* setup the second A32 window */            UNIV_OUT_LONG(UNIVERSE_VSI4_BS,  VAL_VSI4_BS);            UNIV_OUT_LONG(UNIVERSE_VSI4_BD,  VAL_VSI4_BD);            UNIV_OUT_LONG(UNIVERSE_VSI4_TO,  VAL_VSI4_TO);            UNIV_OUT_LONG(UNIVERSE_VSI4_CTL, VAL_VSI4_CTL);            /* setup the third A32 window */            UNIV_OUT_LONG(UNIVERSE_VSI5_BS,  VAL_VSI5_BS);            UNIV_OUT_LONG(UNIVERSE_VSI5_BD,  VAL_VSI5_BD);            UNIV_OUT_LONG(UNIVERSE_VSI5_TO,  VAL_VSI5_TO);            UNIV_OUT_LONG(UNIVERSE_VSI5_CTL, VAL_VSI5_CTL);#endif	/* ANY_BRDS_IN_CHASSIS_NOT_RMW */#endif	/* SM_OFF_BAORD */	    }	}