#define UNIVERSE_VSI6_BS        UNIVERSE_ADRS(0xFbc)#define UNIVERSE_VSI6_BD        UNIVERSE_ADRS(0xFc0)#define UNIVERSE_VSI6_TO        UNIVERSE_ADRS(0xFc4)#define UNIVERSE_VSI7_CTL       UNIVERSE_ADRS(0xFcc)#define UNIVERSE_VSI7_BS        UNIVERSE_ADRS(0xFd0)#define UNIVERSE_VSI7_BD        UNIVERSE_ADRS(0xFd4)#define UNIVERSE_VSI7_TO        UNIVERSE_ADRS(0xFd8)#define UNIVERSE_VCSR_CLR       UNIVERSE_ADRS(0xFF4)#define UNIVERSE_VCSR_SET       UNIVERSE_ADRS(0xFF8)#define UNIVERSE_VCSR_BS        UNIVERSE_ADRS(0xFFC)/* NOW LET'S DEFINE THE BITS FOR THESE REGISTERS *//* PCI MISC0 Register */#define PCI_MISC0_LATENCY_TIMER 0x0000f800      /* max. value for timer *//* PCI Configuration Space Control and Status Register */#define PCI_CSR_MASK            0x007ffc00      /* Reserved bits */#define PCI_CSR_D_PE            (1 << 31)       /* Detected/Clear Parity Error*/#define PCI_CSR_S_SERR          (1 << 30)       /* Signalled SERR#            */#define PCI_CSR_R_MA            (1 << 29)       /* Received Master Abort      */#define PCI_CSR_R_TA            (1 << 28)       /* Received Target Abort      */#define PCI_CSR_S_TA            (1 << 27)       /* Signalled Target Abort     */#define PCI_CSR_DEVSEL_MEDIUM   (1 << 25)       /* Universe is medium speed   */#define PCI_CSR_DP_D            (1 << 24)       /* Master detected/generated  */                                                /* a data parity error        */#define PCI_CSR_TFBBC           (1 << 23)       /* Target Fast Back to Back   */                                                /* Capable (must be ?)        */#define PCI_CSR_MFBBC           (1 << 9)        /* Master Fast Back to Back   */                                                /* Capable (must be 0)        */#define PCI_CSR_SERR_EN         (1 << 8)        /* Enable SERR# drivers       */#define PCI_CSR_WAIT            (1 << 7)        /* Wait Cycle Control         */#define PCI_CSR_PERSP           (1 << 6)        /* Enable Parity Error Resp   */#define PCI_CSR_VGAPS           (1 << 5)        /* VGA Palette Snp (must be 0)*/#define PCI_CSR_MWI_EN          (1 << 4)        /* Enable Memory Write and    */                                                /* Invalidate (must be 0)     */#define PCI_CSR_SC              (1 << 3)        /* Respond to Special Cycles  */                                                /* (must be 0)                */#define PCI_CSR_BM              (1 << 2)        /* Master Enable              */#define PCI_CSR_MS              (1 << 1)        /* Target Memory Enable       */#define PCI_CSR_IOS             (1)             /* Target I/O Enable          *//* PCI Slave Image Control for Registers 0, 1,2, and 3 */#define LSI_CTL_MASK           0x3f380efc      /* Mask bits */#define LSI_CTL_EN             (1 << 31)       /* Enable PCI Slave Image     */#define LSI_CTL_WP             (1 << 30)       /* Enable Posted Writes       */#define LSI_CTL_D8             (0 << 22)       /* Max VME Data Width = 8     */#define LSI_CTL_D16            (1 << 22)       /* Max VME Data Width = 16    */#define LSI_CTL_D32            (2 << 22)       /* Max VME Data Width = 32    */#define LSI_CTL_D64            (3 << 22)       /* Max VME Data Width = 64    */#define LSI_CTL_A16            (0 << 16)       /* VME Address Space A16      */#define LSI_CTL_A24            (1 << 16)       /* VME Address Space A24      */#define LSI_CTL_A32            (2 << 16)       /* VME Address Space A32      */#define LSI_CTL_CSR            (5 << 16)       /* VME Address Space CSR      */#define LSI_CTL_USER1          (6 << 16)       /* VME Address Space USER 1   */#define LSI_CTL_USER2          (7 << 16)       /* VME Address Space USER 2   */#define LSI_CTL_PGM            (1 << 14)       /* Program AM Code            */#define LSI_CTL_DATA           (0 << 14)       /* Data AM Code               */#define LSI_CTL_SUP            (1 << 12)       /* Supervisor AM Code         */#define LSI_CTL_USR            (0 << 12)       /* User AM Code               */#define LSI_CTL_BLK            (1 << 8)        /* Supervisor AM Code         */#define LSI_CTL_SINGLE         (0 << 8)        /* User AM Code               */#define LSI_CTL_PCI_MEM        (0 << 0)        /* PCI Memory Space           */#define LSI_CTL_PCI_IO         (1 << 0)        /* PCI I/O Space              */#define LSI_CTL_PCI_CONFIG     (2 << 0)        /* PCI Type 1 Config Space    *//* PCI Slave Image Base Address Register 0 */#define LSI0_BS_MASK    0x00000fff/* PCI Slave Image Bound Address Register 0 */#define LSI0_BD_MASK    0x00000fff/* PCI Slave Image Translation Offset Register 0 */#define LSI0_TO_MASK    0x00000fff/* PCI Slave Image Base Address Register 1 */#define LSI1_BS_MASK    0x0000ffff/* PCI Slave Image Bound Address Register 1 */#define LSI1_BD_MASK    0x0000ffff/* PCI Slave Image Translation Offset Register 1 */#define LSI1_TO_MASK    0x0000ffff/* PCI Slave Image Base Address Register 2 */#define LSI2_BS_MASK    0x0000ffff/* PCI Slave Image Bound Address Register 2 */#define LSI2_BD_MASK    0x0000ffff/* PCI Slave Image Translation Offset Register 2 */#define LSI2_TO_MASK    0x0000ffff/* PCI Slave Image Base Address Register 3 */#define LSI3_BS_MASK    0x0000ffff/* PCI Slave Image Bound Address Register 3 */#define LSI3_BD_MASK    0x0000ffff/* PCI Slave Image Translation Offset Register 3 */#define LSI3_TO_MASK    0x0000ffff/* PCI Special Cycle Control Register */#define SCYC_CTL_MASK   	(3 << 0)#define SCYC_CTL_DISABLE        (0)             /* Disable Special Cycle Gen  */#define SCYC_CTL_RMW            (1)             /* RMW Special Cycle          */#define SCYC_CTL_ADO            (2)             /* ADO Special Cycle          *//* PCI Special Cycle Address Register */#define SCYC_ADDR_MASK  0xfffffffc/* PCI Miscellaneous Register */#define LMISC_CRT_INFINITE      (0 << 28)       /* Coupled Request Timeout */#define LMISC_CRT_128_USEC      (1 << 28)       /* Coupled Request Timeout */#define LMISC_CRT_256_USEC      (2 << 28)       /* Coupled Request Timeout */#define LMISC_CRT_512_USEC      (3 << 28)       /* Coupled Request Timeout */#define LMISC_CRT_1024_USEC     (4 << 28)       /* Coupled Request Timeout */#define LMISC_CRT_2048_USEC     (5 << 28)       /* Coupled Request Timeout */#define LMISC_CRT_4096_USEC     (6 << 28)       /* Coupled Request Timeout */#define LMISC_CWT_DISABLE       (0 << 24)       /* Coupled Window Timeout     */                                /* Immediate Release after first transaction  */#define LMISC_CWT_16_CLKS       (1 << 24)       /* Coupled Window Timeout     */#define LMISC_CWT_32_CLKS       (2 << 24)       /* Coupled Window Timeout     */#define LMISC_CWT_64_CLKS       (3 << 24)       /* Coupled Window Timeout     */#define LMISC_CWT_128_CLKS      (4 << 24)       /* Coupled Window Timeout     */#define LMISC_CWT_256_CLKS      (5 << 24)       /* Coupled Window Timeout     */#define LMISC_CWT_512_CLKS      (6 << 24)       /* Coupled Window Timeout     *//* * Special PCI Slave Image * - provides access to all of A16 and most of A24 VME Space */#define SLSI_EN                 (1 << 31)       /* Enable PCI Slave Image     */#define SLSI_WP                 (1 << 30)       /* Enable Posted Writes       */#define SLSI_D16                (1 << 20)       /* Max VME Data Width = 16    */#define SLSI_D32                (2 << 20)       /* Max VME Data Width = 32    */#define SLSI_PGM                (1 << 12)       /* Program AM Code            */#define SLSI_DATA               (0 << 12)       /* Data AM Code               */#define SLSI_SUP                (1 << 8)        /* Supervisor AM Code         */#define SLSI_USR                (0 << 8)        /* User AM Code               */#define SLSI_PCI_MEM            (0 << 0)        /* PCI Memory Space           */#define SLSI_PCI_IO             (1 << 0)        /* PCI I/O Space              */#define SLSI_PCI_CONFIG         (2 << 0)        /* PCI Type 1 Config Space    *//* PCI Command Error Log Register */#define L_CMDERR_LOG            (0xf << 28)     /* Command Error Log          */#define L_CMDERR_MASK           0x078fffff      /* Reserved bits */#define L_CMDERR_M_ERR          (1 << 27)       /* Multiple Error Occurred    */#define L_CMDERR_L_STAT         (1 << 23)       /* Logs are valid and halted  */#define L_CMDERR_L_ENABLE       (1 << 23)       /* Clear and Enable Logging   *//* DMA Transfer Control Register */#define DCTL_VALID_BITS_MASK	0x80c7f180#define DCTL_MASK               0x7f380e7f      /* Reserved bits */#define DCTL_L2V                (1 << 31)       /* PCI-to-VME transfer */#define DCTL_L2V_MSK		(1 << 31)#define DCTL_VDW_MSK		(3 << 22)#define DCTL_VAS_MSK		(7 << 16)#define DCTL_PGM_MSK		(3 << 14)#define DCTL_SUPER_MSK		(3 << 12)#define DCTL_VCT_MSK		(1 << 8)#define DCTL_LD64EN_MSK		(1 << 7)#define DCTL_L2V_VME_PCI	(0)		/* VME-to-PCI transfer */#define DCTL_L2V_PCI_VME	(1 << 31)       /* PCI-to-VME transfer */#define DCTL_VDW_8              (0)             /* Maximum data width 8 bits */#define DCTL_VDW_16             (1 << 22)       /* Maximum data width 16 bits */#define DCTL_VDW_32             (2 << 22)       /* Maximum data width 32 bits */#define DCTL_VDW_64             (3 << 22)       /* Maximum data width 64 bits */#define DCTL_VAS_A16            (0)             /* VME address space A16 */#define DCTL_VAS_A24            (1 << 16)       /* VME address space A24 */#define DCTL_VAS_A32            (2 << 16)       /* VME address space A32 */#define DCTL_VAS_USER1          (6 << 16)       /* VME address space User1 */#define DCTL_VAS_USER2          (7 << 16)       /* VME address space User2 */#define DCTL_PGM_DATA           (0)             /* Data AM code */#define DCTL_PGM_PRGM           (1 << 14)       /* Program AM code */#define DCTL_SUPER_USER         (0)             /* Non-privileged AM code */#define DCTL_SUPER_SUP          (1 << 12)       /* Supervisor AM code */#define DCTL_VCT_EN             (1 << 8)        /* Block mode capable */#define DCTL_VCT_SINGLE		0		/* Single cycle only */#define DCTL_VCT_BLK		(1 << 8)        /* Single and Block transfers */#define DCTL_LD64EN             (1 << 7)        /* 64-bit PCI transactions */#define DCTL_LD64EN_32		0		/* 32-bit PCI transactions *//* DMA Transfer Byte Count Register */#define DTBC_MASK       0xff000000#define	DTBC_VALID_BITS_MASK	0x00ffffff/* DMA General Control/Status Register */#define DGCS_MASK               0x00000000      /* Reserved bits */#define DGCS_VALID_BITS_MASK	0xe8ffef6f#define DGCS_CHAIN_MSK		(1 << 27)#define DGCS_VON_MSK		(0xf << 20)#define DGCS_VOFF_MSK		(0xf << 16)#define DGCS_STATUS_MSK		(0xef << 8)#define DGCS_INTR_MSK		(0x6f << 0)#define DGCS_GO                 (1 << 31)       /* Start DMA */#define DGCS_STOP_REQ           (1 << 30)       /* Stop Request */#define DGCS_HALT_REQ           (1 << 29)       /* Halt Request */#define DGCS_CHAIN_DMODE	(0)		/* DMA Direct Mode */#define DGCS_CHAIN_LLMODE       (1 << 27)       /* DMA Linked List Mode */#define DGCS_CHAIN              (1 << 27)       /* DMA chaining */#define DGCS_VON_DONE           (0)             /* Transfer count until done*/#define DGCS_VON_256            (1 << 20)       /* Transfer count 256 bytes */#define DGCS_VON_512            (2 << 20)       /* Transfer count 512 bytes */#define DGCS_VON_1024           (3 << 20)       /* Transfer count 1024 bytes */#define DGCS_VON_2048           (4 << 20)       /* Transfer count 2048 bytes */#define DGCS_VON_4096           (5 << 20)       /* Transfer count 4096 bytes */#define DGCS_VON_8192           (6 << 20)       /* Transfer count 4096 bytes */#define DGCS_VON_16384          (7 << 20)       /* Transfer count 16384 bytes */#define DGCS_VOFF_0             (0)             /* Time off VME bus0 us */#define DGCS_VOFF_16            (1 << 16)       /* Time off VME bus16 us */#define DGCS_VOFF_32            (2 << 16)       /* Time off VME bus32 us */#define DGCS_VOFF_64            (3 << 16)       /* Time off VME bus64 us */#define DGCS_VOFF_128           (4 << 16)       /* Time off VME bus128 us */#define DGCS_VOFF_256           (5 << 16)       /* Time off VME bus256 us */#define DGCS_VOFF_512           (6 << 16)       /* Time off VME bus512 us */#define DGCS_VOFF_1024          (7 << 16)       /* Time off VME bus1024 us */#define DGCS_ACT                (1 << 15)       /* DMA active */#define DGCS_STOP               (1 << 14)       /* DMA stopped */#define DGCS_HALT               (1 << 13)       /* DMA halted */#define DGCS_DONE               (1 << 11)       /* DMA done */#define DGCS_LERR               (1 << 10)       /* PCI bus error */#define DGCS_VERR               (1 << 9)        /* VME bus error */#define DGCS_P_ERR              (1 << 8)        /* Protocol error */#define DGCS_INT_STOP           (1 << 6)        /* Interrupt stop enable */#define DGCS_INT_HALT           (1 << 5)        /* Interrupt halt enable */#define DGCS_INT_DONE           (1 << 3)        /* Interrupt done enable */#define DGCS_INT_LERR           (1 << 2)        /* Interrupt LERR enable */#define DGCS_INT_VERR           (1 << 1)        /* Interrupt VERR enable */#define DGCS_INT_P_ERR          (1)             /* Interrupt protocol enable *//* DMA Linked List Update Enable Register *//* PCI Configuration Base Address Register */#define PCI_BS_SPACE            (1)             /* Memory or I/O power-up *//* PCI Interrupt Enable Register */#define LINT_EN_MASK            0xffff0000      /* Reserved bits */#define LINT_EN_ACFAIL          (1 << 15)       /* Enable Interrupt ACFAIL   */#define LINT_EN_SYSFAIL         (1 << 14)       /* Enable Interrupt SYSFAIL  */#define LINT_EN_SW_INT          (1 << 13)       /* Enable Interrupt SW_INT   */#define LINT_EN_SW_IACK         (1 << 12)       /* Enable Interrupt SW_ACK   */#define LINT_EN_VERR            (1 << 10)       /* Enable Interrupt ACFAIL   */#define LINT_EN_LERR            (1 << 9)        /* Enable Interrupt ACFAIL   */#define LINT_EN_DMA             (1 << 8)        /* Enable Interrupt ACFAIL   */#define LINT_EN_VIRQ7           (1 << 7)        /* Enable Interrupt VME IRQ7 */#define LINT_EN_VIRQ6           (1 << 6)        /* Enable Interrupt VME IRQ6 */#define LINT_EN_VIRQ5           (1 << 5)        /* Enable Interrupt VME IRQ5 */#define LINT_EN_VIRQ4           (1 << 4)        /* Enable Interrupt VME IRQ4 */#define LINT_EN_VIRQ3           (1 << 3)        /* Enable Interrupt VME IRQ3 */#define LINT_EN_VIRQ2           (1 << 2)        /* Enable Interrupt VME IRQ2 */#define LINT_EN_VIRQ1           (1 << 1)        /* Enable Interrupt VME IRQ1 */#define LINT_EN_VOWN            (1 << 0)        /* Enable Interrupt VME OWN *//* PCI Interrupt Status Register */#define LINT_STAT_MASK          0xffff0800      /* Reserved bits */#define LINT_STAT_ACFAIL        (1 << 15)       /* Status Interrupt ACFAIL   */#define LINT_STAT_SYSFAIL       (1 << 14)       /* Status Interrupt SYSFAIL  */#define LINT_STAT_SW_INT        (1 << 13)       /* Status Interrupt SW_INT   */#define LINT_STAT_SW_IACK       (1 << 12)       /* Status Interrupt SW_ACK   */#define LINT_STAT_VERR          (1 << 10)       /* Status Interrupt ACFAIL   */#define LINT_STAT_LERR          (1 << 9)        /* Status Interrupt ACFAIL   */#define LINT_STAT_DMA           (1 << 8)        /* Status Interrupt ACFAIL   */#define LINT_STAT_VIRQ7         (1 << 7)        /* Status Interrupt VME IRQ7 */#define LINT_STAT_VIRQ6         (1 << 6)        /* Status Interrupt VME IRQ6 */#define LINT_STAT_VIRQ5         (1 << 5)        /* Status Interrupt VME IRQ5 */#define LINT_STAT_VIRQ4         (1 << 4)        /* Status Interrupt VME IRQ4 */#define LINT_STAT_VIRQ3         (1 << 3)        /* Status Interrupt VME IRQ3 */#define LINT_STAT_VIRQ2         (1 << 2)        /* Status Interrupt VME IRQ2 */#define LINT_STAT_VIRQ1         (1 << 1)        /* Status Interrupt VME IRQ1 */#define LINT_STAT_VOWN          (1 << 0)        /* Status Interrupt VME OWN */#define LINT_STAT_CLEAR		0xf7ff		/* clear all interrupts */#define LINT_STAT_INT_MASK	0xf7ff		/* mask received interrupts */#define LINT_STAT_FAIL_MASK     0x0000c000      /* mask for sysfail,acfail *//* PCI Interrupt MAP Register 0 */#define LINT_MAP0_MASK  0x88888888/* PCI Interrupt MAP Register 1 */#define LINT_MAP1_MASK  0x8888f888/* VMEbus Interrupt Enable Register */#define VINT_EN_MASK            0xfe0f17ff#define VINT_EN_VME_SW7         (1 << 31)       /* generate interrupt - U2 */#define VINT_EN_VME_SW6         (1 << 30)       /* generate interrupt - U2 */#define VINT_EN_VME_SW5         (1 << 29)       /* generate interrupt - U2 */#define VINT_EN_VME_SW4         (1 << 28)       /* generate interrupt - U2 */#define VINT_EN_VME_SW3         (1 << 27)       /* generate interrupt - U2 */#define VINT_EN_VME_SW2         (1 << 26)       /* generate interrupt - U2 */#define VINT_EN_VME_SW1         (1 << 25)       /* generate interrupt - U2 */#define VINT_EN_SW_INT          (1 << 12)       /* SW_INT interrupt generate */#define VINT_EN_VERR            (1 << 10)       /* VERR interrupt generate */#define VINT_EN_LERR            (1 << 9)        /* LERR enable */#define VINT_EN_DMA             (1 << 8)        /* DMA enable */#define VINT_EN_LINT7           (1 << 7)        /* LINT7 enable */#define VINT_EN_LINT6           (1 << 6)        /* LINT6 enable */#define VINT_EN_LINT5           (1 << 5)        /* LINT5 enable */#define VINT_EN_LINT4           (1 << 4)        /* LINT4 enable */#define VINT_EN_LINT3           (1 << 3)        /* LINT3 enable */#define VINT_EN_LINT2           (1 << 2)        /* LINT2 enable */#define VINT_EN_LINT1           (1 << 1)        /* LINT1 enable */#define VINT_EN_LINT0           (1)             /* LINT0 enable *//* VMEbus Interrupt Status Register */