?? universe.h
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#define VINT_STAT_MASK 0xfe0f17ff#define VINT_STAT_VME_SW7 (1 << 31) /* interrupt active - U2 */#define VINT_STAT_VME_SW6 (1 << 30) /* interrupt active - U2 */#define VINT_STAT_VME_SW5 (1 << 29) /* interrupt active - U2 */#define VINT_STAT_VME_SW4 (1 << 28) /* interrupt active - U2 */#define VINT_STAT_VME_SW3 (1 << 27) /* interrupt active - U2 */#define VINT_STAT_VME_SW2 (1 << 26) /* interrupt active - U2 */#define VINT_STAT_VME_SW1 (1 << 25) /* interrupt active - U2 */#define VINT_STAT_SW_INT (1 << 12) /* SW_INT interrupt active */#define VINT_STAT_VERR (1 << 10) /* VERR interrupt active */#define VINT_STAT_LERR (1 << 9) /* LERR interrupt active */#define VINT_STAT_DMA (1 << 8) /* DMA interrupt active */#define VINT_STAT_LINT7 (1 << 7) /* LINT7 interrupt active */#define VINT_STAT_LINT6 (1 << 6) /* LINT6 interrupt active */#define VINT_STAT_LINT5 (1 << 5) /* LINT5 interrupt active */#define VINT_STAT_LINT4 (1 << 4) /* LINT4 interrupt active */#define VINT_STAT_LINT3 (1 << 3) /* LINT3 interrupt active */#define VINT_STAT_LINT2 (1 << 2) /* LINT2 interrupt active */#define VINT_STAT_LINT1 (1 << 1) /* LINT1 interrupt active */#define VINT_STAT_LINT0 (1) /* LINT0 interrupt active */#define VINT_STAT_CLEAR 0x17ff /* clear outgoing VME intrs. *//* VMEbus Interrupt Map Register 0 */#define VINT_MAP0_MASK 0x77777777#define VINT_MAP0_MAPPING 0x76543210/* VMEbus Interrupt Map Register 1 */#define VINT_MAP1_MASK 0x00070777#define VINT_MAP1_DMA_MASK 0x00000007#define VINT_MAP1_LERR_MASK 0x00000070#define VINT_MAP1_VERR_MASK 0x00000700#define VINT_MAP1_SW_INT_MASK 0x00070000#define VINT_MAP1_DMA_LVL_1 0x01#define VINT_MAP1_DMA_LVL_2 0x02#define VINT_MAP1_DMA_LVL_3 0x03#define VINT_MAP1_DMA_LVL_4 0x04#define VINT_MAP1_DMA_LVL_5 0x05#define VINT_MAP1_DMA_LVL_6 0x06#define VINT_MAP1_DMA_LVL_7 0x07/* VMEbus Interrupt Status/ID Out Register */#define STATID_MASK 0x1ffffff/* VMEbus IRQ1 Status/ID Register */#define V1_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus IRQ2 Status/ID Register */#define V2_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus IRQ3 Status/ID Register */#define V3_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus IRQ4 Status/ID Register */#define V4_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus IRQ5 Status/ID Register */#define V5_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus IRQ6 Status/ID Register */#define V6_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus IRQ7 Status/ID Register */#define V7_STATID_ERR (1 << 8) /* Bus Error during IACK *//* VMEbus Master Control Register */#define MAST_CTL_MASK 0x0003ef00 /* Reserved bits */#define MAST_CTL_RTRY_FOREVER (0 << 28) /* Max Retries before PCI err*/#define MAST_CTL_PWON_128 (0 << 24) /* Posted Write VME Xfer Cnt */#define MAST_CTL_PWON_256 (1 << 24) /* Posted Write VME Xfer Cnt */#define MAST_CTL_PWON_512 (2 << 24) /* Posted Write VME Xfer Cnt */#define MAST_CTL_PWON_1024 (3 << 24) /* Posted Write VME Xfer Cnt */#define MAST_CTL_PWON_2048 (4 << 24) /* Posted Write VME Xfer Cnt */#define MAST_CTL_PWON_4096 (5 << 24) /* Posted Write VME Xfer Cnt */#define MAST_CTL_VRL0 (0 << 22) /* VMEbus Request Level */#define MAST_CTL_VRL1 (1 << 22) /* VMEbus Request Level */#define MAST_CTL_VRL2 (2 << 22) /* VMEbus Request Level */#define MAST_CTL_VRL3 (3 << 22) /* VMEbus Request Level */#define MAST_CTL_VRM_FAIR (1 << 21) /* FAIR Request Mode */#define MAST_CTL_VRM_DEMAND (0 << 21) /* Demand Request Mode */#define MAST_CTL_VREL_RWD (0 << 20) /* Release When Done */#define MAST_CTL_VREL_ROR (1 << 20) /* Release on Request */#define MAST_CTL_VOWN (1 << 19) /* Acquire and Hold VMEbus */#define MAST_CTL_VOWN_ACK (1 << 18) /* VMEbus bus held */#define MAST_CTL_PABS_32 (0 << 12) /* 32 Byte PCI Aligned Burst */#define MAST_CTL_PABS_64 (1 << 12) /* 64 Byte PCI Aligned Burst */#define MAST_CTL_PABS_128 (1 << 12) /* 64 Byte PCI Aligned Burst *//* Miscellaneous Control Register */#define MISC_CTL_MASK 0x0820ffff /* Reserved bits */#define MISC_CTL_VBTO_DISABLE (0 << 28) /* Forever VMEbus Timeout */#define MISC_CTL_VBTO_16USEC (1 << 28) /* 16 Usec VMEbus Timeout */#define MISC_CTL_VBTO_32USEC (2 << 28) /* 32 Usec VMEbus Timeout */#define MISC_CTL_VBTO_64USEC (3 << 28) /* 64 Usec VMEbus Timeout */#define MISC_CTL_VBTO_128USEC (4 << 28) /* 128 Usec VMEbus Timeout */#define MISC_CTL_VBTO_256USEC (5 << 28) /* 256 Usec VMEbus Timeout */#define MISC_CTL_VBTO_512USEC (6 << 28) /* 512 Usec VMEbus Timeout */#define MISC_CTL_VBTO_1024USEC (7 << 28) /* 1024 Usec VMEbus Timeout */#define MISC_CTL_VARB_PRIORITY (1 << 26) /* Priority Arbitration Mode */#define MISC_CTL_VARB_RROBIN (0 << 26) /* Round Robin Arbitration */#define MISC_CTL_VARBTO_DISABLE (0 << 24) /* Round Robin Arbitration */#define MISC_CTL_VARBTO_16USEC (1 << 24) /* Round Robin Arbitration */#define MISC_CTL_VARBTO_256USEC (2 << 24) /* Round Robin Arbitration */#define MISC_CTL_SW_LRST (1 << 23) /* Software PCI Reset */#define MISC_CTL_SW_SRST (1 << 22) /* Software VMEbus Sysreset */#define MISC_CTL_BI_MODE (1 << 20) /* */#define MISC_CTL_ENGBI (1 << 19) /* */#define MISC_CTL_RESCIND (1 << 18) /* Rescinding DTACK Enable */#define MISC_CTL_NO_RESCIND (0 << 18) /* Rescinding DTACK Disable */#define MISC_CTL_SYSCON (1 << 17) /* Universe is SysController */#define MISC_CTL_NOT_SYSCON (0 << 17) /* Universe not SysController */#define MISC_CTL_V64AUTO (1 << 16) /* Initiate VME64 Auto ID *//* Miscellaneous Status Register */#define MISC_STAT_LCL_SIZE_32 (0 << 30) /* PCI Bus is 32 bits */#define MISC_STAT_LCL_SIZE_64 (1 << 30) /* PCI Bus is 64 bits */#define MISC_STAT_DY4AUTO (1 << 27) /* DY4 Auto ID Enable */#define MISC_STAT_MYBBSY_NEGATED (1 << 21) /* Universe Bus Busy Negated */#define MISC_STAT_DY4DONE (1 << 19) /* DY4 Auto ID is Done */#define MISC_STAT_TXFE (1 << 18) /* Transmit FIFO Empty */#define MISC_STAT_RXFE (1 << 17) /* Receive FIFO Empty *//* VMEbus Slave Image Control 0-7 */#define VSI_CTL_EN (1 << 31) /* Image Enable */#define VSI_CTL_PWEN (1 << 30) /* Posted Write Enable */#define VSI_CTL_PREN (1 << 29) /* Prefetch Read Enable */#define VSI_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */#define VSI_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */#define VSI_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */#define VSI_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/#define VSI_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */#define VSI_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */#define VSI_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */#define VSI_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/#define VSI_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*/#define VSI_CTL_LD64EN (1 << 7) /* Enable 64-bit PCI bus Xfer */#define VSI_CTL_LLRMW (1 << 6) /* Enable PCI lock of VME RMW */#define VSI_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */#define VSI_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */#define VSI_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space *//* VMEbus Slave Image 0 Control Mask */#define VSI0_CTL_MASK 0x1f08ff3c /* Reserved Bits *//* VMEbus Slave Image 0 Base Address Register */#define VSI0_BS_MASK 0x00000fff/* VMEbus Slave Image 0 Bound Address Register */#define VSI0_BD_MASK 0x00000fff/* VMEbus Slave Image 0 Translation Offset Register */#define VSI0_TO_MASK 0x00000fff/* VMEbus Slave Image 1 Control Mask */#define VSI1_CTL_MASK 0x1f08ff3c /* Reserved Bits *//* VMEbus Slave Image 1 Base Address Register */#define VSI1_BS_MASK 0x0000ffff/* VMEbus Slave Image 1 Bound Address Register */#define VSI1_BD_MASK 0x0000ffff/* VMEbus Slave Image 1 Translation Offset Register */#define VSI1_TO_MASK 0x0000ffff/* VMEbus Slave Image 2 Control Mask */#define VSI2_CTL_MASK 0x1f08ff3c /* Reserved Bits *//* VMEbus Slave Image 2 Base Address Register */#define VSI2_BS_MASK 0x0000ffff/* VMEbus Slave Image 2 Bound Address Register */#define VSI2_BD_MASK 0x0000ffff/* VMEbus Slave Image 2 Translation Offset Register */#define VSI2_TO_MASK 0x0000ffff/* VMEbus Slave Image 3 Control Mask */#define VSI3_CTL_MASK 0x1f08ff3c /* Reserved Bits *//* VMEbus Slave Image 3 Base Address Register */#define VSI3_BS_MASK 0x0000ffff/* VMEbus Slave Image 3 Bound Address Register */#define VSI3_BD_MASK 0x0000ffff/* VMEbus Slave Image 3 Translation Offset Register */#define VSI3_TO_MASK 0x0000ffff/* VMEbus Slave Image 4 Control Mask */#define VSI4_CTL_MASK 0xe0f700c3/* VMEbus Slave Image 4 Base Address Register */#define VSI4_BS_MASK 0xfffff000/* VMEbus Slave Image 4 Bound Address Register */#define VSI4_BD_MASK 0xfffff000/* VMEbus Slave Image 4 Translation Offset Register */#define VSI4_TO_MASK 0xfffff000/* VMEbus Slave Image 5 Control Mask */#define VSI5_CTL_MASK 0xe0f700c3/* VMEbus Slave Image 5 Base Address Register */#define VSI5_BS_MASK 0xffff0000/* VMEbus Slave Image 5 Bound Address Register */#define VSI5_BD_MASK 0xffff0000/* VMEbus Slave Image 5 Translation Offset Register */#define VSI5_TO_MASK 0xffff0000/* VMEbus Slave Image 6 Control Mask */#define VSI6_CTL_MASK 0xe0f700c3/* VMEbus Slave Image 6 Base Address Register */#define VSI6_BS_MASK 0xffff0000/* VMEbus Slave Image 6 Bound Address Register */#define VSI6_BD_MASK 0xffff0000/* VMEbus Slave Image 6 Translation Offset Register */#define VSI6_TO_MASK 0xffff0000/* VMEbus Slave Image 7 Control Mask */#define VSI7_CTL_MASK 0xe0f700c3/* VMEbus Slave Image 7 Base Address Register */#define VSI7_BS_MASK 0xffff0000/* VMEbus Slave Image 7 Bound Address Register */#define VSI7_BD_MASK 0xffff0000/* VMEbus Slave Image 7 Translation Offset Register */#define VSI7_TO_MASK 0xffff0000/* VMEbus Register Access Image Control Register */#define VRAI_CTL_EN (1 << 31) /* Image Enable */#define VRAI_CTL_AM_DATA (1 << 22) /* Respond to Data AM Code */#define VRAI_CTL_AM_PGM (2 << 22) /* Respond to Prog AM Code */#define VRAI_CTL_AM_SUPER (2 << 20) /* Respond to Superv AM Code */#define VRAI_CTL_AM_USER (1 << 20) /* Respond to Non-Priv AM Code*/#define VRAI_CTL_VAS_A16 (0 << 16) /* Respond to VME A16 */#define VRAI_CTL_VAS_A24 (1 << 16) /* Respond to VME A24 */#define VRAI_CTL_VAS_A32 (2 << 16) /* Respond to VME A32 */#define VRAI_CTL_VAS_USER1 (6 << 16) /* Respond to VME Space User 1*/#define VRAI_CTL_VAS_USER2 (7 << 16) /* Respond to VME Space User 2*//* @prb *//* VMEbus CSR Control Register */#define VCSR_CTL_EN (1 << 31) /* Image Enable */#define VCSR_CTL_LAS_MEM (0 << 0) /* PCIbus Memory Space */#define VCSR_CTL_LAS_IO (1 << 0) /* PCIbus I/O Space */#define VCSR_CTL_LAS_CFG (2 << 0) /* PCIbus Config Space *//* VMEbus AM Code Error Log */#define V_AMERR_MASK 0x07ffffff /* Reserved bits */#define V_AMERR_IACK (1 << 25) /* */#define V_AMERR_M_ERR (1 << 24) /* */#define V_AMERR_V_STAT (1 << 23) /* *//* VMEbus CSR Bit Clear Register */#define VCSR_CLR_MASK 0x1fffffff /* Reserved bits */#define VCSR_CLR_RESET (1 << 31) /* Negate PRST */#define VCSR_CLR_SYSFAIL (1 << 30) /* Negate SysFail */#define VCSR_CLR_FAIL (1 << 29) /* Board has Failed *//* VMEbus CSR Bit Set Register */#define VCSR_SET_RESET (1 << 31) /* Assert PRST */#define VCSR_SET_SYSFAIL (1 << 30) /* Assert SysFail */#define VCSR_SET_FAIL (1 << 29) /* Board has Failed *//* VMEbus CSR Bit Clear Register */#define VCSR_BS_MASK 0x3ffffff /* Reserved bits */#ifdef __cplusplus }#endif#endif /* INCuniverseh */?? 快捷鍵說(shuō)明
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