/* mv2100.h - Motorola PowerPlus board header *//* Copyright 1984-2001 Wind River Systems, Inc. *//* Copyright 1996,1997,1998,1999 Motorola, Inc. All Rights Reserved *//*modification history--------------------01r,16sep01,dat  Use of WRS_ASM macro01q,15jun00,dmw  updated following WRS code review.01p,07jul99,srr  remove erroneous i2c address for second SPD EEPROM.01o,21jun99,srr  added support for running PCI Auto Config in bootrom only.01n,04jun99,rhk  removed netif defines, added A24 slave window support, 		 re-arranged the address map to make VME space contiguous.01m,20apr99,rhk  change to support UNIVERSE in non-autoconfig. mode.01l,16apr99,rhk  changed PCI_xxx names, offset VME and dynamic PCI mem		 addresses from base of PCI mem space, moved configurable PCI		 space size defines to config.h, changed VME LM define names		 to be consistent with other VME define names.01k,08apr99,dmw  added VPD defines.01j,05apr99,rhk  removed DVT defines, changed base addresses for dynamic PCI		 memory space and Kahlua registers for CHRP addressing.01i,23mar99,rhk  re-ordered the VMEbus Geographical Address register bits		 based on rev. 1.1 of MVME2100 Programming Manual.01h,12mar99,rhk  added Shared Memory support, added UNIVERSE II location		 monitor/mailbox interrupt support, modified VME window		 defines.01g,24feb99,rhk  added PCI autconfig. support, changed to new PCI_XXX                 naming conventions.01f,18feb99,srr  cleaned up serial port and NVRAM defines.01e,10feb99,rhk  updated the interrupt level/vector defines for mv2100.01d,09feb99,rhk  added/cleaned up PCI defines.01c,26jan99,rhk  added board register definitions.01b,21jan99,rhk  removed legacy 2600 items.01a,11dec98,srr  created. (from ver 02h, mv2600.h)*//*This file contains I/O addresses and related constants for theMotorola PowerPlus VME board. */#ifndef	INCmv2100h#define	INCmv2100h#ifdef __cplusplusextern "C" {#endif /* __cplusplus */#include "kahlua.h"/* board revision values */#define BOARD_REV_A		1#define BOARD_REV_B		2#define BOARD_REV_C		3/* CPU type */#define CPU_TYPE                ((vxPvrGet() >> 16) & 0xffff)#define CPU_TYPE_601		0x01		/* PPC 601 CPU */#define CPU_TYPE_602		0x02		/* PPC 602 CPU */#define CPU_TYPE_603		0x03		/* PPC 603 CPU */#define CPU_TYPE_603E           0x06   		/* PPC 603e CPU */#define CPU_TYPE_603EK		0x81		/* PPC 603e-Kahlua CPU */#define CPU_TYPE_603P           0x07    	/* PPC 603p CPU */#define CPU_TYPE_750            0x08    	/* PPC 750 CPU */#define CPU_TYPE_604		0x04		/* PPC 604 CPU */#define CPU_TYPE_604E		0x09		/* PPC 604e CPU */#define CPU_TYPE_604R		0x0A		/* PPC 604r CPU */#define CPU_TYPE_8240		0x81		/* PPC 603e-Kahlua CPU *//* Vital Product Data Support */#define NUM_SDRAM_BANKS		4	/* Number of possible SDRAM banks */#define SPD_EEPROM_ADRS0	0xa0	/* i2c address of first SPD EEPROM */#if (MV2100_REV == BOARD_REV_A)#   define VPD_BRD_EEPROM_ADRS	0xae	/* i2c address of board's SROM */#endif /* (MV2100_REV == BOARD_REV_A) */#if (MV2100_REV == BOARD_REV_C)#   define VPD_BRD_EEPROM_ADRS	0xa8	/* i2c address of board's SROM */#endif /* (MV2100_REV == BOARD_REV_C) */#define VPD_BRD_OFFSET		0	/* offset into board's eeprom for 					   vpd data */#define EEPROM_TYPE_KAHLUA	0#define I2C_DRV_TYPE		EEPROM_TYPE_KAHLUA /* I2C driver type flag */#define VPD_PKT_LIMIT		25	/* Max number of packets expected */#define DEFAULT_PCI_CLOCK	33333333#define DEFAULT_BUS_CLOCK	100000000#define DEFAULT_INTERNAL_CLOCK	250000000#define DEFAULT_PRODUCT_ID	"Unknown"#define MHZ	    		1000000#define NANO2SEC    		1000000000  /* num of nanoseconds per second */#define INCLUDE_PCI		/* always include pci *//* Boot Line parameters are stored in the 2nd 256 byte block */#undef	NV_BOOT_OFFSET#define NV_BOOT_OFFSET		256 /* skip 1st 256 bytes */#define NV_RAM_SIZE    		BBRAM_SIZE		#define NV_RAM_ADRS    		((char *) BBRAM_ADRS)#define NV_RAM_INTRVL           1/* PCI-PCI Bridge setup values */#define P2P_IO_SPACE_BASE_ADRS    ((P2P_IO_BASE & 0x0000F000) >> 8)#define P2P_IO_SPACE_LIMIT_ADRS   ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0x0000F000)#define	P2P_IO_HI16_BASE_ADRS     ((P2P_IO_BASE & 0xFFFF0000) >> 16)#define	P2P_IO_HI16_LIMIT_ADRS    ((P2P_IO_BASE + P2P_IO_SIZE - 1) & 0xFFFF0000)#define P2P_NPMEM_SPACE_BASE_ADRS ((P2P_NONPREF_MEM_BASE & 0xFFFF0000) >> 16)#define P2P_NPMEM_SPACE_LIMIT_ADRS ((P2P_NONPREF_MEM_BASE + \                                     P2P_NONPREF_MEM_SIZE - 1) & 0xFFFF0000)#define P2P_PREF_MEM_BASE_ADRS    ((P2P_PREF_MEM_BASE & 0xFFFF0000) >> 16)#define P2P_PREF_MEM_LIMIT_ADRS ((P2P_PREF_MEM_BASE + P2P_PREF_MEM_SIZE - 1) & \                                 0xFFFF0000)/* PCI I/O function defines */#ifndef _ASMLANGUAGE#ifndef PCI_IN_BYTE#   define PCI_IN_BYTE(x)          sysPciInByte (x)    IMPORT  UINT8                  sysPciInByte  (UINT32 address);#endif /* PCI_IN_BYTE */#ifndef PCI_IN_WORD#   define PCI_IN_WORD(x)          sysPciInWord (x)    IMPORT  UINT16                 sysPciInWord  (UINT32 address);#endif /* PCI_IN_WORD */#ifndef PCI_IN_LONG#   define PCI_IN_LONG(x)          sysPciInLong (x)    IMPORT  UINT32                 sysPciInLong  (UINT32 address);#endif /* PCI_IN_LONG */#ifndef PCI_OUT_BYTE#   define PCI_OUT_BYTE(x,y)       sysPciOutByte (x,y)    IMPORT  void                   sysPciOutByte (UINT32 address, UINT8  data);#endif /* PCI_OUT_BYTE */#ifndef PCI_OUT_WORD#   define PCI_OUT_WORD(x,y)       sysPciOutWord (x,y)    IMPORT  void                   sysPciOutWord (UINT32 address, UINT16 data);#endif /* PCI_OUT_WORD */#ifndef PCI_OUT_LONG#   define PCI_OUT_LONG(x,y)       sysPciOutLong (x,y)    IMPORT  void                   sysPciOutLong (UINT32 address, UINT32 data);#endif /* PCI_OUT_WORD */#endif  /* _ASMLANGUAGE *//* Cache Line Size - 32 32-bit value = 128 bytes */#define PCI_CLINE_SZ		0x20/* Latency Timer value - 255 PCI clocks */#define PCI_LAT_TIMER		0xff/* clock rates */#define SPEED66MHZ		66#define SPEED83MHZ		83#define SPEED100MHZ		100/* Calculate Memory Bus Rate in Hertz */#define MEMORY_BUS_SPEED        (sysGetBusSpd())/* System clock (decrementer counter) frequency determination */#define DEC_CLOCK_FREQ          MEMORY_BUS_SPEED/* CIO clocks and stuff */#define	CIO_RESET_DELAY		5000#define	ZCIO_HZ			2500000 /* 2.5 MHz clock */#define	CIO_INT_VEC		9#define	Z8536_TC		ZCIO_HZ/* * The PowerPC Decrementer is used as the system clock. * It is always included in this BSP.  The following defines * are used by the system clock library. */#define SYS_CLK_RATE_MIN  	10		/* minimum system clock rate */#define SYS_CLK_RATE_MAX  	5000		/* maximum system clock rate *//* * This macro returns the positive difference between two signed ints. * Useful for determining delta between two successive decrementer reads. */#define DELTA(a,b)		( abs((int)a - (int)b) )/* * Auxiliary Clock support is an optional feature that is not supported * by all BSPs.  The following defines are used by the aux clock library. */#define AUX_CLK_RATE_MIN  	40		/* min auxiliary clock */#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate *//* * Shared Memory Interrupt Type. * Interrupt this target with a 1-byte write mailbox. * SM_INT_ARG1 uses VME_A32 space,  * SM_INT_ARG2 defines the address based on procNum,  * SM_INT_ARG3 (value) is defined to be backward compatible with earlier BSPs. */#define SM_INT_ARG1 		VME_AM_EXT_SUP_DATA#define SM_INT_ARG2 		(VME_LM_MSTR_BUS + \				 (sysProcNumGet() * VME_LM_SLV_SIZE))#define SM_INT_ARG3		0x80/*  * Common I/O synchronizing instructions  * * Only SYNC is used for the 603e processors.  The "eieio" instruction * is treated as a NOP on the 603e. */#ifndef SYNC#  define SYNC  		WRS_ASM (" sync")#endif  /* SYNC *//* BSP configuration error policy */#define CONTINUE_EXECUTION      0       /* Tolerate VPD/Configuration errors */#define EXIT_TO_SYSTEM_MONITOR  1       /* Transfer to System Monitor */#ifdef TOLERATE_CONFIG_ERRORS#  define DEFAULT_BSP_ERROR_BEHAVIOR  CONTINUE_EXECUTION#else#  define DEFAULT_BSP_ERROR_BEHAVIOR  EXIT_TO_SYSTEM_MONITOR#endif /* TOLERATE_CONFIG_ERRORS *//*  * The following macros define access to PCI and ISA space from the CPU * and the base addresses of PCI and ISA spaces on the bus (from the CPU * point of view). * These macros contain the correct starting addresses and sizes * for use in the BSP and user programming. * */#ifdef CHRP_ADRS_MAP/* Access to PCI ISA I/O space */#  define ISA_MSTR_IO_LOCAL	0xfe000000#  define ISA_MSTR_IO_BUS	0x00000000              /* 0 based addressing */#  define ISA_MSTR_IO_SIZE 	0x00010000              /* 64 kbytes max. *//* Access to PCI I/O space */#  define PCI_MSTR_IO_LOCAL	0xfe800000#  define PCI_MSTR_IO_BUS	0x00800000		#  define PCI_MSTR_IO_SIZE	0x00400000		/* 4MB max. *//* Access to PCI nonprefetchable memory space (including ISA memory space) */#  define PCI_MSTR_MEMIO_LOCAL	0xfd000000#  define PCI_MSTR_MEMIO_BUS	0x00000000		/* 0 based addressing *//* Access to PCI memory space */#  define PCI_MSTR_MEM_LOCAL    0x80000000		/* base of PCI mem */#  define PCI_MSTR_MEM_BUS      PCI_MSTR_MEM_LOCAL      /* CHRP mode uses */							/* pass through addr */#  define PCI_MSTR_MEM_SIZE     0x7d000000		/* Total size of PCI */							/* Memory space, */							/* don't change this */#else /* PReP map *//* Access to PCI ISA I/O space */#  define ISA_MSTR_IO_LOCAL   	0x80000000#  define ISA_MSTR_IO_BUS     	0x00000000              /* 0 based addressing */#  define ISA_MSTR_IO_SIZE 	0x00010000              /* 64 kbytes max. *//* Access to PCI I/O space */#  define PCI_MSTR_IO_LOCAL     0x81000000#  define PCI_MSTR_IO_BUS       0x01000000              /* 0 base + ISA range *//* Access to PCI nonprefetchable memory space (including ISA memory space) */#  define PCI_MSTR_MEMIO_LOCAL  0xc0000000#  define PCI_MSTR_MEMIO_BUS    0x00000000              /* 0 based addressing *//* Access to PCI memory space */#  define PCI_MSTR_MEM_LOCAL    0xc1000000#  define PCI_MSTR_MEM_BUS      0x01000000		/* 0 base + ISA MEM */#  define PCI_MSTR_MEM_SIZE     0x3e000000		/* Total size of PCI */                                                        /* Memory space, */                                                        /* don't change this */	#endif /* CHRP_ADRS_MAP *//* setup the dynamic PCI memory space for CHRP and PReP */#ifdef CHRP_ADRS_MAP#  define PCI_DYNAMIC_MEM_LOCAL	(PCI_MSTR_MEM_LOCAL + 0x72000000)#  define PCI_DYNAMIC_MEM_BUS	PCI_DYNAMIC_MEM_LOCAL	/* 1-1 translation */#else#  define PCI_DYNAMIC_MEM_LOCAL (PCI_MSTR_MEM_LOCAL + 0x0)#  define PCI_DYNAMIC_MEM_BUS   (PCI_MSTR_MEM_BUS + 0x0)#endif /* CHRP_ADRS_MAP *//*  * The following describes the additional address spaces used for  * PCI space configuration on the Kahlua processor.  The addresses  * for each type of mapping (CHRP or PReP) are fixed and cannot be * modified. */#ifdef CHRP_ADRS_MAP/* additional PCI CHRP memory map defines (as seen from the CPU) */#  define PCI_MSTR_PRIMARY_CAR      	0xfec00000  /* PCI config address reg */#  define PCI_MSTR_PRIMARY_CAR_SIZE	0x00001000  /* use 4KB page tbl entry */#  define PCI_MSTR_PRIMARY_CDR      	0xfee00000  /* PCI config data reg */#  define PCI_MSTR_PRIMARY_CDR_SIZE	0x00001000  /* use 4KB page tbl entry */#  define PCI_MSTR_IACK_BASE_ADRS	0xfef00000  /* PCI interrupt acknowl */#  define PCI_MSTR_IACK_SIZE		0x00001000  /* use 4KB page tbl entry */#  define PCI_MSTR_IACK_WNDW_ADRS	PCI_MSTR_IACK_BASE_ADRS#else /* PReP map *//* additional PCI PREP memory map defines (as seen from the CPU) */#  define PCI_MSTR_PRIMARY_CAR	   (ISA_MSTR_IO_LOCAL + 0xcf8)  /* PCI CAR */#  define PCI_MSTR_PRIMARY_CDR	   (ISA_MSTR_IO_LOCAL + 0xcfc)  /* PCI CDR */#  define PCI_MSTR_DIRECT_MAP_ADRS (ISA_MSTR_IO_LOCAL + 0x00800000) /* base */						    /* of direct PCI config */						    /* space access */#  define PCI_MSTR_DIRECT_SIZE	   0x00800000       /* 8MB */#  define PCI_MSTR_IACK_BASE_ADRS  0xbffffff0	    /* PCI interrupt acknowl */#  define PCI_MSTR_IACK_SIZE       0x00001000	    /* use 4KB page tbl entry */#  define PCI_MSTR_IACK_WNDW_ADRS  0xbffff000#  define PCI_CHRP_PRIMARY_CAR	   0xfec00000	    /* CHRP CAR and CDR adrs */#  define PCI_CHRP_PRIMARY_CDR	   0xfee00000	    /* for switch to PReP */#endif /* CHRP_ADRS_MAP */#define FLASH_BASE_ADRS         0xff000000#define FLASH_MEM_SIZE          0x01000000/* defines for PCI AUTO_CONFIG */#define ISA_LEGACY_SIZE 	0x00004000/* * PCI MASTER MEMORY WINDOW LIMITS for sysBusProbe * * These values are strictly defined by the base memory addresses and window * sizes of the spaces defined above.  These values must be correct for the * sysBusProbe() memory range checks for the PCI bus to work properly. */#ifdef CHRP_ADRS_MAP#  define PCI_MSTR_LO_ADRS	PCI_MSTR_MEM_LOCAL#  define PCI_MSTR_HI_ADRS	(PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE)#else /* PReP map */#  define PCI_MSTR_LO_ADRS	ISA_MSTR_IO_LOCAL#  define PCI_MSTR_HI_ADRS	(PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE)#endif /* CHRP_ADRS_MAP *//*  * Map PCI memory access to local CPU space * * PCI_SLV_MEM_LOCAL  - Base address of Local CPU space * PCI_SLV_MEM_BUS    - Base address of local memory as seen from PCI Bus * PCI_SLV_MEM_SIZE   - Size of Window for Local space access *//* * The macro PCI_SLV_MEM_BUS sets the base value for PCI Mem space access of * local memory.  A PCI memory device that puts this address onto the bus will * access local memory at the address specified by PCI_SLV_MEM_LOCAL */#ifdef CHRP_ADRS_MAP#  define PCI_SLV_MEM_BUS	0x00000000#else /* PReP map */#  define PCI_SLV_MEM_BUS       0x80000000#endif /* CHRP_ADRS_MAP */#define PCI2DRAM_BASE_ADRS	PCI_SLV_MEM_BUS	 /* needed for usrNetwork.c *//* * The macro PCI_SLV_MEM_LOCAL is the base at which local memory will appear * in CPU space. */#define PCI_SLV_MEM_LOCAL       LOCAL_MEM_LOCAL_ADRS/* * The macro PCI_SLV_MEM_SIZE specify the range of PCI