/* config.h - Motorola PowerPlus board configuration header *//* Copyright 1984-2002 Wind River Systems, Inc. *//* Copyright 1996,1997,1998,1999,2000 Motorola, Inc. All Rights Reserved *//*modification history--------------------01s,16apr02,dat  Update for T2.2 release01r,25oct01,mil  Fixed build error when no networking is included (SPR 64423).01q,13jul00,rcs	 defined FLASH_BOOT so ROM base will be soldered flash.01p,17jun00,dat  version 1.2/1 for WRS release01o,16feb00,rhk  bump revision to 0.3 for vxMemProbe and I2C fixes.01n,22dec99,rhk  modify comments relating to FLASH_BOOT and ROM addrs,  		 changed RAM_HIGH_ADRS to 0x00800000.01m,07jul99,srr  bump revision to 0.2 for rev C board addressing fix.01l,25jun99,srr  add STANDALONE_NET for shared memory in Tornado 2.01k,22jun99,srr  add INCLUDE_BSD for shared memory in Tornado 2,                 add BSP_VER_1_2 and undef INCLUDE_ECC by default.01j,04jun99,rhk  removed all defines related to netif, made all PCI interrupt		 priorities the same, setup A24 slave access defines.01i,28may99,dmw  Enabled ECC and floating point and removed standalone.01h,07may99,dmw  added define for soldered flash boot images.01g,28apr99,rhk  changed the minimum size of PCI MEMIO and IO windows.01f,16apr99,rhk  added size defines for configurable PCI windows.01e,05apr99,rhk  legacy mv2600 cleanup.01d,12mar99,rhk  added Shared Memory support.01c,24feb99,rhk  added support for PCI autoconfig.01b,18feb99,srr  cleaned up serial port defines.01a,11dec98,srr  created. (from ver 02f, mv2600/config.h)*//*DESCRIPTIONThis file contains the configuration parameters for theMotorola PowerPlus architectureNotes:1. The MVME2100 is built around the Motorola Kahlua PowerPCmicrocontroller.  The MVME2100 is a VMEbus-based singleboard computer.  Key features of the MVME2100 includeeither one 32-bit PMC expansion slot, one Type 1 and twoType 2 PC-MIP expansion slots, or two Type 1 and twoType 2 PC-MIP expansion slots, 32, 64, 96MB of ECCsynchronous DRAM memory, 1MB Boot FLASH ROM, 4 or 8MBexpansion FLASH ROM, one 10/100Base-TX Ethernet port,and one front panel accessible asynchronous serial port.2. The MVME2100 defaults to the PowerPC Common HardwareReference Platform (CHRP) address map.  This address mapallows for a large PCI memory address space.  This largePCI memory address space is needed for VMEbus addressability.The BSP is designed to work by default with the CHRP address map,if the PReP (PowerPC Reference Platform) address map is desired,then undef CHRP_ADRS_MAP.*/#ifndef	INCconfigh#define	INCconfigh#ifdef __cplusplusextern "C" {#endif/* The following defines must precede configAll.h *//* BSP version/revision identification */#define BSP_VER_1_1     1#define BSP_VER_1_2     1#define BSP_VERSION     "1.2"#define BSP_REV         "/2"		/* T2.2 release *//* PRIMARY INCLUDES */#include "configAll.h"/* defines */#if (CPU == PPC603)#   define DEFAULT_BOOT_LINE \	"dc(0,0)host:/tornado/mv2100/vxWorks h=90.0.0.1 e=90.0.0.2 u=vxworks"#   define WRONG_CPU_MSG "A PPC603 VxWorks image cannot run on a PPC604!\n";#endif	/* (CPU == PPC604) *//* define the board revision */#define MV2100_REV	BOARD_REV_C/* define, if SHOW routines are to be included */#undef INCLUDE_SHOW_ROUTINES/* * If any slave board in the chassis cannot generate a VMEbus * RMW, or the master board cannot translate an incoming VMEbus * RMW into an atomic operation, define ANY_BRDS_IN_CHASSIS_NOT_RMW * else * All slave boards are generating a VMEbus RMW, and the master * board can translate an incoming VMEbus RMW into an atomic * operation, so undef ANY_BRDS_IN_CHASSIS_NOT_RMW */#define	ANY_BRDS_IN_CHASSIS_NOT_RMW/* * Default board configurations * * If a supported feature is desired, *         change to: #define * If a feature is not desired or not supported *         change to: #undef * * NOTE: Not all functionality is supported on all boards */#ifdef  MV2100#    undef	INCLUDE_CACHE_L2	/* [NOT AVAILABLE] */#    undef	INCLUDE_SCSI		/* [NOT AVAILABLE] */#    define	INCLUDE_AUX_CLK		/* Auxiliary clock support */#    undef	INCLUDE_ECC		/* Kahlua ECC */#    undef	INCLUDE_VME_DMA		/* VME DMA support */#    define	INCLUDE_HW_FP		/* Kahlua 1.0 doesn't have FP */#    define     INCLUDE_PCI_AUTOCONF    /* PCI auto configuration */#    define     FLASH_BOOT		/* select ROM base */#    define	INCLUDE_END		/* Enhanced Network Driver */#    undef	A24_SLV_WINDOW		/* open an A24 window on proc. 0 */#endif/* Address mapping select, CHRP is enabled by default, #undef selects PReP */#define	CHRP_ADRS_MAP/* MMU and Cache options */#define	INCLUDE_MMU_BASIC       /* bundled mmu support */#undef	USER_D_CACHE_MODE#define	USER_D_CACHE_MODE       (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)/* timestamp option not included by default;  #define to include it */#undef  INCLUDE_TIMESTAMP/* De-select unused (default) network drivers selected in configAll.h */#undef  INCLUDE_EX              /* include Excelan Ethernet interface */#undef  INCLUDE_ENP             /* include CMC Ethernet interface*//* SCSI support */#ifdef  INCLUDE_SCSI#define INCLUDE_SCSI2		/* Use SCSI2 library, not SCSI1 */#define INCLUDE_SCSI_BOOT	/* include ability to boot from SCSI */#define INCLUDE_DOSFS		/* file system to be used */#undef	SCSI_AUTO_CONFIG	/* scan bus on startup */#undef	SCSI_WIDE_ENABLE	/* enable wide SCSI on MVME761-011 only */#define	SYS_SCSI_CONFIG		/* call sysScsiConfig in sysScsi.c */#endif  /* INCLUDE_SCSI *//* PCI bus numbers for secondary and subordinate buses */#define PCI_SECONDARY_BUS       1#define PCI_SUBORD_BUS          1#define PCI_MAX_BUS             2       /* Max. number of PCI buses in system *//* PMC Span (PCI Bridge) configuration parameters */#undef	INCLUDE_PMC_SPAN        /* PMC Span support not included by default *//* PMC Span configuration values */#define	P2P_IO_BASE              0x01060000	/* PCI I/O window */#define	P2P_IO_SIZE              0x00040000#define	P2P_PREF_MEM_BASE        0x02000000	/* PCI prefetch mem window */#define	P2P_PREF_MEM_SIZE        0x01000000#define	P2P_PREF_HI32_BASE       0x00000000	/* hi 32 bits of address */#define	P2P_NONPREF_MEM_BASE     0x03000000	/* PCI non-prefech mem window */#define P2P_NONPREF_MEM_SIZE	 0x01000000#define P2P_CACHE_LINE_SIZE      8		/* cache line size */#define P2P_PRIM_LATENCY         0		/* latency *//* serial parameters */#undef	NUM_TTY#define	NUM_TTY			N_SIO_CHANNELS/* * Auxiliary Clock support is an optional feature that is not supported * by all BSPs. */#ifndef  INCLUDE_AUX_CLK#    undef INCLUDE_SPY#else#    define INCLUDE_SPY#endif /* INCLUDE_AUX_CLK *//* Shared-memory Backplane Network parameters *//* * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane * driver and the auto address setup which are defined in configAll.h.  To * exclude them uncomment the following lines: * * #undef  INCLUDE_SM_NET * #undef  INCLUDE_SM_SEQ_ADDR */#if defined(INCLUDE_SM_NET)#   define STANDALONE_NET#   define INCLUDE_NET_SHOW#   define INCLUDE_BSD#endif /* defined(INCLUDE_SM_NET) *//* * Changing SM_OFF_BOARD to TRUE also requires changing * SM_ANCHOR_ADRS and SM_MEM_ADRS appropriately. */#define SM_OFF_BOARD	FALSE#undef  SM_ANCHOR_ADRS#define SM_ANCHOR_ADRS  ((sysProcNumGet() == 0) ? \        ((char*) (LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET)) : \        ((char*) (VME_A32_MSTR_LOCAL + SM_ANCHOR_OFFSET)))#define SM_INT_TYPE		SM_INT_MAILBOX_1	/* or SM_INT_NONE *//* * The following defines are only used by the master. * If SM_OFF_BOARD == FALSE, these values are used * by the master's UNIVERSE_II window definitions, so * they need to be on a 64K byte boundary. * The slave only uses the "Anchor" address. */#define SM_MEM_ADRS		0x00010000	/* Start of actual SM region */#define SM_MEM_SIZE		0x00020000#define SM_OBJ_MEM_ADRS		(SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */#define SM_OBJ_MEM_SIZE		0x00010000#define	INCLUDE_VME		/* undef to exclude VME support *//* * Local Memory definitions * * By default, the available DRAM memory is sized at bootup (LOCAL_MEM_AUTOSIZE * is defined).  If auto-sizing is not selected, make certain that * LOCAL_MEM_SIZE is set to the actual amount of memory on the board. * By default, it is set to the minimum memory configuration: 16 MB. * Failure to do so can cause unpredictable system behavior! */#define	LOCAL_MEM_AUTOSIZE			/* undef for fixed size */#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at zero */#define LOCAL_MEM_SIZE		0x01000000	/* Default: Min memory: 16MB */#define RAM_HIGH_ADRS		0x00800000  	/* RAM address for ROM boot */#define RAM_LOW_ADRS		0x00100000	/* RAM address for kernel *//* user reserved memory, see sysMemTop() */#define USER_RESERVED_MEM	(0)	/* number of reserved bytes */#define	FLASH_TEXT_ADRS	(FLASH_BASE_ADRS + 0x100) /* 0xff000100 *//* * The constants ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS  * are defined in config.h, Makefile. * All definitions for these constants must be identical. */#ifdef  FLASH_BOOT#    define	ROM_BASE_ADRS	FLASH_BASE_ADRS	 /* base address of flash */#    define	ROM_TEXT_ADRS	FLASH_TEXT_ADRS#else#   define	ROM_BASE_ADRS	0xfff00000	/* base addr of socketed ROM */#   define	ROM_TEXT_ADRS	(ROM_BASE_ADRS + 0x100)#endif /* FLASH_BOOT */#define	ROM_SIZE		0x00100000	/* 1 Meg ROM space *//* Setup the sizes of the various PCI window spaces *//*  * Size of the PReP PCI I/O space,  * up to 0x3f000000 bytes (1GB - 16MB ) are available for this space. * Note: this size is used in setting up the page table entry for this * PCI space, so setting this to a large value will tie up DRAM. */#ifndef CHRP_ADRS_MAP#  define PCI_MSTR_IO_SIZE      0x00400000      /* 4MB window by default */#endif/* * Size of the PCI nonprefetchable memory space ( includes ISA memory space) * up to 16MB is available. * Need at least 4MB if using PCI-PCI bridging. */#define PCI_MSTR_MEMIO_SIZE	0x00400000	/* 4MB default *//*  * Size of the dynamic PCI memory space for CHRP and PReP, * maximum size for the window is: * 183MB for CHRP * 0x17000000 for PReP. */#define PCI_DYNAMIC_MEM_SIZE	0x02000000	/* 32MB default *//* * VME A32 master window, * * The standard window size (as shipped) is 128 MB.  This is the largest * size recommended for use with TLBs and is the largest size allowed with * extended VME addressing disabled.  Use of only BAT registers can increase * the size to 1 GB.  For larger sizes, TLBs and BATs must be used together. * * Memory address granularity is 64 KB for TLBs while BATs are restricted to