/* kahlua.h - Kahlua chip header file *//* Copyright 1984-2000 Wind River Systems, Inc. *//* Copyright 1996-2000 Motorola, Inc. All Rights Reserved *//*modification history--------------------01f,08feb00,rhk  added defines for Kahlua PCI Status Register Bits.01e,04jun99,rhk  file format changes.01d,08apr99,dmw  added the upper start and end memory controller reg offsets.01c,05apr99,rhk  changed KAHLUA_EUMB_BASE to a fixed address.01b,12feb99,rhk  fixed the kahlua register address defines.01a,26jan99,rhk  created for the mv2100 BSP.*//*This file contains Base address defines, register offsets and bitdefinitions for the the Kahlua chip*/#ifndef INCkahluah#define INCkahluah#ifdef __cplusplusextern "C" {#endif#ifdef  _ASMLANGUAGE#define CAST(x)#elsetypedef volatile UINT32 VUINT32;        /* volatile unsigned word */typedef volatile UINT16 VUINT16;        /* volatile unsigned halfword */typedef volatile UINT8 VUINT8;          /* volatile unsigned byte */#define CAST(x) (x)#endif  /* _ASMLANGUAGE *//* *	IBC Extensions to Standard PCI Config Header register offsets */#define PCI_CFG_IBC_INTR_ROUTE	0x44#define PCI_CFG_IBC_ARB_CTL	0x83/* PCI Arbiter Control Register bit definitions */#define ARB_CTL_GAT		(1 << 7)#define ARB_CTL_TIMEOUT_TIMER	(1 << 2)#define ARB_CTL_BUS_LOCK	(1 << 0)/* Aux Clock Legacy */#define DESTINATION_CPU0	0x00000001/* Kahlua Base addresses */#define KAHLUA_EUMB_SIZE	0x00100000#define KAHLUA_EUMB_BASE	KAHLUA_REGISTERS_BASE/*  * Base addresses for the compnents of the Embedded Utilities Memory * Block.  These form the base addresses for the bulk of the Kahlua * registers and are offset from the KAHLUA_EMBEDDED_UTILS_MEM_BLOCK_BASE */#define KAHLUA_I2O_BASE		(KAHLUA_EUMB_BASE + 0x00000)#define KAHLUA_DMA_BASE		(KAHLUA_EUMB_BASE + 0x01000)#define KAHLUA_ATU_BASE		(KAHLUA_EUMB_BASE + 0x02000)#define KAHLUA_I2C_BASE		(KAHLUA_EUMB_BASE + 0x03000)#define KAHLUA_EPIC_BASE	(KAHLUA_EUMB_BASE + 0x40000)#define KAHLUA_DIAG_REGS_BASE	(KAHLUA_EUMB_BASE + 0x80000)#define EPIC_BASE	KAHLUA_EPIC_BASE#define DIAG_BASE	KAHLUA_DIAG_REGS_BASE/* hardware implementation register extensions for Kahlua */#define HID2	1011		/* HID2 is SPR 1011 *//*  * HID0 bit modifications for the Kahlua * The original bit definitions for HID0 are in arch/ppc/ppc603.h */#undef _PPC_HID0_EICE			/* not used in 603e CPUs */#undef _PPC_HID0_SIED			/* not used in 603e CPUs */#undef _PPC_HID0_BHTE			/* not used in 603e CPUs */#define _PPC_HID0_IFEM	 0x00000080	/* instruction fetch enable M bit */#define _PPC_HID0_FBIOB  0x00000010	/* force branch indirect on bus */#define _PPC_HID0_ABE	 0x00000008	/* address broadcast enable */#define _PPC_HID0_NOOPTI 0x00000001	/* NO-OP touch instructions *//* HID1 bit definitions */#define _PPC_HID1_PC0	 0x80000000	/* PLL config bit 0 (read only) */#define _PPC_HID1_PC1    0x40000000     /* PLL config bit 1 (read only) */#define _PPC_HID1_PC2    0x20000000     /* PLL config bit 2 (read only) */#define _PPC_HID1_PC3    0x10000000     /* PLL config bit 3 (read only) */#define _PPC_HID1_PC4    0x08000000     /* PLL config bit 4 (read only) */#define _PPC_HID1_FPD	 0x00000001	/* floating point disabled *//* HID2 bit definitions */#define _PPC_HID2_SFP		0x00010000	/* speed for power */#define _PPC_HID2_IWLCK_MASK	0x0000e000	/* instr cache way lock bits */#define _PPC_HID2_IWLCK_SHFT	15#define _PPC_HID2_DWLCK_MASK	0x000000e0	/* data cache way lock bits */#define _PPC_HID2_DWLCK_SHFT	7/* Kahlua Message Unit (I2O) Registers */#define KAHLUA_I2O_PIC		(CAST(VUINT8 *)  (KAHLUA_I2O_BASE + 0x0009))#define KAHLUA_I2O_SUB_CLASS	(CAST(VUINT8 *)  (KAHLUA_I2O_BASE + 0x000a))#define KAHLUA_I2O_BASE_CLASS	(CAST(VUINT8 *)  (KAHLUA_I2O_BASE + 0x000b))#define KAHLUA_I2O_IMR0		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0050))#define KAHLUA_I2O_IMR1		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0054))#define KAHLUA_I2O_OMR0		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0058))#define KAHLUA_I2O_OMR1		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x005c))#define KAHLUA_I2O_ODBR		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0060))#define KAHLUA_I2O_IDBR		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0068))#define KAHLUA_I2O_IMISR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0100))#define KAHLUA_I2O_IMMR		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0104))#define KAHLUA_I2O_IFHPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0120))#define KAHLUA_I2O_IFTPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0128))#define KAHLUA_I2O_IPHPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0130))#define KAHLUA_I2O_IPTPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0138))#define KAHLUA_I2O_OFHPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0140))#define KAHLUA_I2O_OFTPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0148))#define KAHLUA_I2O_OPHPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0150))#define KAHLUA_I2O_OPTPR	(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0158))#define KAHLUA_I2O_MUCR		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0164))#define KAHLUA_I2O_QBAR		(CAST(VUINT32 *) (KAHLUA_I2O_BASE + 0x0170))/* Kahlua DMA Registers */#define KAHLUA_DMA_0_MODE	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0100))#define KAHLUA_DMA_0_STATUS	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0104))#define KAHLUA_DMA_0_ADR_DESC	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0108))#define KAHLUA_DMA_0_SRC_ADR	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0110))#define KAHLUA_DMA_0_DEST_ADR	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0118))#define KAHLUA_DMA_0_BYTE_CNT	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0120))#define KAHLUA_DMA_0_NSER_ADR	(CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0124))#define KAHLUA_DMA_1_MODE       (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0200))#define KAHLUA_DMA_1_STATUS     (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0204))#define KAHLUA_DMA_1_ADR_DESC   (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0208))#define KAHLUA_DMA_1_SRC_ADR    (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0210))#define KAHLUA_DMA_1_DEST_ADR   (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0218))#define KAHLUA_DMA_1_BYTE_CNT   (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0220))#define KAHLUA_DMA_1_NSER_ADR   (CAST(VUINT32 *) (KAHLUA_DMA_BASE + 0x0224))/* Kahlua Address Tranlation Unit (ATU) Registers */#define KAHLUA_ATU_OMBAR	(CAST(VUINT32 *) (KAHLUA_ATU_BASE + 0x0300))#define KAHLUA_ATU_OTWR		(CAST(VUINT32 *) (KAHLUA_ATU_BASE + 0x0308))#define KAHLUA_ATU_ITWR		(CAST(VUINT32 *) (KAHLUA_ATU_BASE + 0x0310))/* Kahlua I2C Registers */#define KAHLUA_I2C_ADR_REG	(CAST(VUINT32 *) (KAHLUA_I2C_BASE + 0x0000))#define KAHLUA_I2C_FREQ_DIV_REG	(CAST(VUINT32 *) (KAHLUA_I2C_BASE + 0x0004))#define KAHLUA_I2C_CONTROL_REG	(CAST(VUINT32 *) (KAHLUA_I2C_BASE + 0x0008))#define KAHLUA_I2C_STATUS_REG	(CAST(VUINT32 *) (KAHLUA_I2C_BASE + 0x000c))#define KAHLUA_I2C_DATA_REG	(CAST(VUINT32 *) (KAHLUA_I2C_BASE + 0x0010))/* Kahlua EPIC Registers */#define EPIC_FEATURE_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01000))#define EPIC_GLOBAL_CONFIG_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01020))#define EPIC_INTR_CONFIG_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01030))#define EPIC_VENDOR_ID_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01080))#define EPIC_PROCESSOR_INIT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01090))#define EPIC_SPUR_VEC_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x010e0))#define EPIC_TIMER_FREQ_REG		(CAST(VUINT32 *)(EPIC_BASE + 0x010f0))#define EPIC_TIMER0_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01100))#define EPIC_TIMER0_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01110))#define EPIC_TIMER0_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01120))#define EPIC_TIMER0_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01130))#define EPIC_TIMER1_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01140))#define EPIC_TIMER1_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01150))#define EPIC_TIMER1_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01160))#define EPIC_TIMER1_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01170))#define EPIC_TIMER2_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01180))#define EPIC_TIMER2_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x01190))#define EPIC_TIMER2_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011a0))#define EPIC_TIMER2_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011b0))#define EPIC_TIMER3_CUR_CNT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011c0))#define EPIC_TIMER3_BASE_CT_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011d0))#define EPIC_TIMER3_VEC_PRI_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011e0))#define EPIC_TIMER3_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x011f0))#define EPIC_EXT_SRC0_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10000))#define EPIC_EXT_SRC0_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10010))#define EPIC_EXT_SRC1_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10020))#define EPIC_EXT_SRC1_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10030))#define EPIC_EXT_SRC2_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10040))#define EPIC_EXT_SRC2_DEST_REG 		(CAST(VUINT32 *) (EPIC_BASE + 0x10050))#define EPIC_EXT_SRC3_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10060))#define EPIC_EXT_SRC3_DEST_REG 		(CAST(VUINT32 *) (EPIC_BASE + 0x10070))#define EPIC_SER_SRC0_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10200))#define EPIC_SER_SRC0_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10210))#define EPIC_SER_SRC1_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10220))#define EPIC_SER_SRC1_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10230))#define EPIC_SER_SRC2_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10240))#define EPIC_SER_SRC2_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10250))#define EPIC_SER_SRC3_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10260))#define EPIC_SER_SRC3_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10270))#define EPIC_SER_SRC4_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10280))#define EPIC_SER_SRC4_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10290))#define EPIC_SER_SRC5_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x102a0))#define EPIC_SER_SRC5_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x102b0))#define EPIC_SER_SRC6_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x102c0))#define EPIC_SER_SRC6_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x102d0))#define EPIC_SER_SRC7_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x102e0))#define EPIC_SER_SRC7_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x102f0))#define EPIC_SER_SRC8_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10300))#define EPIC_SER_SRC8_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10310))#define EPIC_SER_SRC9_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10320))#define EPIC_SER_SRC9_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10330))#define EPIC_SER_SRC10_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10340))#define EPIC_SER_SRC10_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10350))#define EPIC_SER_SRC11_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10360))#define EPIC_SER_SRC11_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10370))#define EPIC_SER_SRC12_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x10380))#define EPIC_SER_SRC12_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x10390))#define EPIC_SER_SRC13_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x103a0))#define EPIC_SER_SRC13_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x103b0))#define EPIC_SER_SRC14_VEC_PRI_REG 	(CAST(VUINT32 *) (EPIC_BASE + 0x103c0))#define EPIC_SER_SRC14_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x103d0))#define EPIC_SER_SRC15_VEC_PRI_REG	(CAST(VUINT32 *) (EPIC_BASE + 0x103e0))#define EPIC_SER_SRC15_DEST_REG		(CAST(VUINT32 *) (EPIC_BASE + 0x103f0))#define EPIC_I2C_INTR_VEC_SRC		(CAST(VUINT32 *) (EPIC_BASE + 0x11020))#define EPIC_I2C_INTR_DEST		(CAST(VUINT32 *) (EPIC_BASE + 0x11030))#define EPIC_DMA_CHAN0_INTR_VEC_SRC	(CAST(VUINT32 *) (EPIC_BASE + 0x11040))#define EPIC_DMA_CHAN0_INTR_DEST	(CAST(VUINT32 *) (EPIC_BASE + 0x11050))#define EPIC_DMA_CHAN1_INTR_VEC_SRC	(CAST(VUINT32 *) (EPIC_BASE + 0x11060))#define EPIC_DMA_CHAN1_INTR_DEST	(CAST(VUINT32 *) (EPIC_BASE + 0x11070))#define EPIC_MSG_UNIT_INTR_VEC_SRC	(CAST(VUINT32 *) (EPIC_BASE + 0x110c0))#define EPIC_MSG_UNIT_INTR_DEST		(CAST(VUINT32 *) (EPIC_BASE + 0x110d0))#define EPIC_CUR_TASK_PRI_REG 		(CAST(VUINT32 *) (EPIC_BASE + 0x20080))#define EPIC_IACK_REG			(CAST(VUINT32 *) (EPIC_BASE + 0x200a0))#define EPIC_EOI_REG			(CAST(VUINT32 *) (EPIC_BASE + 0x200b0))/* Kahlua Diagnostic Registers */