/* kahluaMemParam.h - Memory Controller Parameter Initialization definitions *//* Copyright 1998-1999 Motorola, Inc. *//*modification history--------------------01d,12jun02,kab  SPR 74987: cplusplus protection01c,07jul99,srr  Remove unused shift and mask definitions.01b,28may99,dmw  Updated to WindRiver coding standards.01a,09mar99,dmw  written. (from mv2400 hawkSmc.h 01a,13jan99)*/#ifndef INC_KAHLUAMEMPARAM_H#define INC_KAHLUAMEMPARAM_H#ifdef __cplusplus    extern "C" {#endif/*DESCRIPTIONtypedefs and defines common to all memory controllers */#define MEMORY_WAIT_CLK_1	1#define MEMORY_WAIT_CLK_2	2#define MEMORY_WAIT_CLK_3	3#define MEMORY_WAIT_CLK_4	4#define MEMORY_WAIT_CLK_5	5#define MEMORY_WAIT_CLK_6	6#define MEMORY_WAIT_CLK_7	7#define SDRAM_SIZE_0		(0<<0)	/* DRAM bank size 0MB */#define SDRAM_SIZE_32_4MX16	(1<<0)	/* DRAM bank size 32MB(4Mx16) */#define SDRAM_SIZE_64_8MX8	(2<<0)	/* DRAM bank size 64MB(8Mx8) */#define SDRAM_SIZE_64_8MX16	(3<<0)	/* DRAM bank size 64MB(8Mx16) */#define SDRAM_SIZE_128_16MX4	(4<<0)	/* DRAM bank size 128MB(16Mx4) */#define SDRAM_SIZE_128_16MX8	(5<<0)	/* DRAM bank size 128MB(16Mx8) */#define SDRAM_SIZE_128_16MX16	(6<<0)	/* DRAM bank size 128MB(16Mx16) */#define SDRAM_SIZE_256_32MX4	(7<<0)	/* DRAM bank size 256MB(32Mx4) */#define SDRAM_SIZE_256_32MX8	(8<<0)	/* DRAM bank size 256MB(32Mx8) */#define SDRAM_SIZE_512_64MX4	(9<<0)	/* DRAM bank size 512MB(64Mx4) */#define SDRAM_SIZE_RSRVD0	(10<<0)	/* DRAM bank size reserved */#define SDRAM_SIZE_RSRVD1	(11<<0)	/* DRAM bank size reserved */#define SDRAM_SIZE_RSRVD2	(12<<0)	/* DRAM bank size reserved */#define SDRAM_SIZE_RSRVD3	(13<<0)	/* DRAM bank size reserved */#define SDRAM_SIZE_RSRVD4	(14<<0)	/* DRAM bank size reserved *//* * Memory Interface control structure template.  Values to program * Kahlua Memory Interface with. */typedef struct {   UINT MCCR1;		/* Memory Control Configuration Reg 1 */   UINT MCCR2;		/* Memory Control Configuration Reg 2 */   UINT MCCR3;		/* Memory Control Configuration Reg 3 */   UINT MCCR4;		/* Memory Control Configuration Reg 4 */   UINT MSR3_2_1_0;	/* Memory Starting Address Reg 3/2/1/0 */   UINT MSR7_6_5_4;	/* Memory Starting Address Reg 7/6/5/4 */   UINT MSER3_2_1_0;	/* Extended Mem Starting Address Reg 3/2/1/0 */   UINT MSER7_6_5_4;	/* Extended Mem Starting Address Reg 7/6/5/4 */   UINT MER3_2_1_0;	/* Memory Ending Address Reg 3/2/1/0 */   UINT MER7_6_5_4;	/* Memory Ending Address Reg 7/6/5/4 */   UINT MEER3_2_1_0;	/* Extended Memory Ending Address Reg 3/2/1/0 */   UINT MEER7_6_5_4;	/* Extended Memory Ending Address Reg 7/6/5/4 */   UCHAR MPMR;		/* Memory Page Mode Reg */   UCHAR MBER;		/* Memory Bank Enable Reg */   UINT sdramSize;	/* Total memory found */   UCHAR clkFrequency;	/* Operating clock frequency */} sramConfigReg;#define KAHLUA_MEM_ADDR_SHIFT		20#define KAHLUA_MEM_BANK_INDEX		8#define KAHLUA_MCC3_BSTORE_DFLT		0xF #define KAHLUA_MCC4_BSTORE_DFLT		0x3 #define KAHLUA_MCC4_BURST_LEN		0x2 #define KAHLUA_MCC4_BURST_LEN		0x2 #define KAHLUA_MCC4_BSTPRE_DFLT		0xF/* Default Memory Interface settings 32Mbytes, 83.33Mhz */#define KAHLUA_SDRAM_MCCR1_DEFAULT	0x53140000#define KAHLUA_SDRAM_MCCR2_DEFAULT	0x0A2C1419#define KAHLUA_SDRAM_MCCR3_DEFAULT	0xFA300000#define KAHLUA_SDRAM_MCCR4_DEFAULT	0x470C323F#define KAHLUA_SDRAM_MSR3_2_1_0_DFLT	0x00000000#define KAHLUA_SDRAM_MSR7_6_5_4_DFLT	0x00000000#define KAHLUA_SDRAM_MSER3_2_1_0_DFLT	0x00000000#define KAHLUA_SDRAM_MSER7_6_5_4_DFLT	0x00000000#define KAHLUA_SDRAM_MER3_2_1_0_DFLT	0x00001F00#define KAHLUA_SDRAM_MER7_6_5_4_DFLT	0x00000000#define KAHLUA_SDRAM_MEER3_2_1_0_DFLT	0x00000000#define KAHLUA_SDRAM_MEER7_6_5_4_DFLT	0x00000000#define KAHLUA_SDRAM_MPMR_DEFAULT	0x80#define KAHLUA_SDRAM_MBER_DEFAULT	0x02/* Defines for the memory ending address register */#define KAHLUA_SDRAM_SIZE_32	(1<<26)	/* DRAM bank size 32MB */#define KAHLUA_SDRAM_SIZE_64	(1<<27)	/* DRAM bank size 64MB */#define KAHLUA_SDRAM_SIZE_32_ER	((0x20-1)<<8)	/* 32MB end addr */#define KAHLUA_SDRAM_SIZE_64_ER	((0x40-1)<<0)	/* 64MB end addr */#define KAHLUA_SDRAM_SIZE_96_ER	((0x40-1)<<0)|((0x60-1)<<8))/* 96MB end addr */#define KAHLUA_SDRAM_SIZE_64_SR	((0x40)<<8)	/* 64MB start addr bank 1 *//* * ROM timing worst case memory access.  This constant is based on the * slowest ROM device on the memory bus.  This value was interpreted * from on a memory interface configuration table supplied by the hardware * engineer.  This value is used to calulate PGMAX. */#define KAHLUA_ROM_WCMA		0x4e/* Refressh rates in uSecs. */#define KAHLUA_REFINT_REFR_NORMAL	15600#define KAHLUA_REFINT_REFR_REDUCED_DIV4	3900#define KAHLUA_REFINT_REFR_REDUCED_DIV2	7800#define KAHLUA_REFINT_REFR_EXTENDED_2X	31300#define KAHLUA_REFINT_REFR_EXTENDED_4X	62500#define KAHLUA_REFINT_REFR_EXTENDED_8X	125000#define SDRAM_CL3_DEFAULT	 1      /* SDRAM Ctrl Reg cl3 default */#define SDRAM_TRC_DEFAULT	11      /* SDRAM Ctrl Reg tRC default */#define SDRAM_TRAS_DEFAULT	 7      /* SDRAM Ctrl Reg tRAS default */#define SDRAM_SWR_DPL_DEFAULT	 1      /* SDRAM Ctrl Reg swr_dpl default */#define SDRAM_TDP_DEFAULT	 2      /* SDRAM Ctrl Reg tDP default */#define SDRAM_TRP_DEFAULT	 3      /* SDRAM Ctrl Reg tRP default */#define SDRAM_TRCD_DEFAULT	 3      /* SDRAM Ctrl Reg tRCD default */#define SDRAM_TCYC_DEFAULT       0      /* SDRAM Cycle Time default */#define SDRAM_DIMM_TYPE_DEFAULT  0      /* SDRAM Dimm Config Type default */#ifdef __cplusplus    }#endif#endif /* INC_KAHLUAMEMPARAM_H */