/************************************************************************************
	FILENAME:	C641X.h
	DESIGNER:	DaiZhanBo
	COMPANY:	SEED
************************************************************************************/
#ifndef _Register
#define _Register


/* INTERNAL MEMORY CONTROL REGISTERS */

/* CACHE CONFIGURATION REGISTER */
#define CCFG (int *) 0x01840000
/* L2 ALLOCATION REGISTER 0 */
#define L2ALLOC0 (int *) 0x01842000
/* L2 ALLOCATION REGISTER 1 */
#define L2ALLOC1 (int *) 0x01842004
/* L2 ALLOCATION REGISTER 2 */
#define L2ALLOC2 (int *) 0x01842008
/* L2 ALLOCATION REGISTER 3 */
#define L2ALLOC3 (int *) 0x0184200C
/* L2 FLUSH BASE ADDRESS REGISTER */
#define L2FBAR (int *) 0x01844000
/* L2 FLUSH WORD COUNT REGISTER */
#define L2CBAR (int *) 0x01844004
/* L2 CLEAN BASE ADDRESS REGISTER */
#define L2FWC (int *) 0x01844010
/* L2 CLEAN WORD COUNT REGISTER */
#define L2CWC (int *) 0x01844014
/* L1P FLUSH BASE ADDRESS REGISTER */
#define L1PFBAR (int *) 0x01844020
/* L1P FLUSH WORD COUNT REGISTER */
#define L1PFWC (int *) 0x01844024
/* L1D FLUSH BASE ADDRESS REGISTER */
#define L1DFBAR (int *) 0x01844030
/* L1D FLUSH WORD COUNT REGISTER */
#define L1DFWC (int *) 0x01844034
/* L2 FLUSH REGISTER */
#define L2FLUSH (int *) 0x01845000
/* L2 CLEAN REGISTER */
#define L2CLEAN (int *) 0x01845004

/* CONTROL EMIFB CE0 RANGE 60000000H~60FFFFFFH */
#define MAR96 (int *) 0x01848180
/* CONTROL EMIFB CE0 RANGE 61000000H~61FFFFFFH */
#define MAR97 (int *) 0x01848184
/* CONTROL EMIFB CE0 RANGE 62000000H~62FFFFFFH */
#define MAR98 (int *) 0x01848188
/* CONTROL EMIFB CE0 RANGE 63000000H~63FFFFFFH */
#define MAR99 (int *) 0x0184818c
/* CONTROL EMIFB CE1 RANGE 64000000H~64FFFFFFH */
#define MAR100 (int *) 0x01848190
/* CONTROL EMIFB CE1 RANGE 65000000H~65FFFFFFH */
#define MAR101 (int *) 0x01848194
/* CONTROL EMIFB CE1 RANGE 66000000H~66FFFFFFH */
#define MAR102 (int *) 0x01848198
/* CONTROL EMIFB CE1 RANGE 67000000H~67FFFFFFH */
#define MAR103 (int *) 0x0184819c
/* CONTROL EMIFB CE2 RANGE 68000000H~68FFFFFFH */
#define MAR104 (int *) 0x018481A0
/* CONTROL EMIFB CE2 RANGE 69000000H~69FFFFFFH */
#define MAR105 (int *) 0x018481A4
/* CONTROL EMIFB CE2 RANGE 6A000000H~6AFFFFFFH */
#define MAR106 (int *) 0x018481A8
/* CONTROL EMIFB CE2 RANGE 6B000000H~6BFFFFFFH */
#define MAR107 (int *) 0x018481Ac
/* CONTROL EMIFB CE3 RANGE 6C000000H~6CFFFFFFH */
#define MAR108 (int *) 0x018481B0
/* CONTROL EMIFB CE3 RANGE 6D000000H~6DFFFFFFH */
#define MAR109 (int *) 0x018481B4
/* CONTROL EMIFB CE3 RANGE 6E000000H~6EFFFFFFH */
#define MAR110 (int *) 0x018481B8
/* CONTROL EMIFB CE3 RANGE 6F000000H~6FFFFFFFH */
#define MAR111 (int *) 0x018481Bc

/* CONTROL EMIFA CE0 RANGE 80000000H~80FFFFFFH */
#define MAR128 (int *) 0x01848200
/* CONTROL EMIFA CE0 RANGE 81000000H~81FFFFFFH */
#define MAR129 (int *) 0x01848204
/* CONTROL EMIFA CE0 RANGE 82000000H~82FFFFFFH */
#define MAR130 (int *) 0x01848208
/* CONTROL EMIFA CE0 RANGE 83000000H~83FFFFFFH */
#define MAR131 (int *) 0x0184820c
/* CONTROL EMIFA CE0 RANGE 84000000H~84FFFFFFH */
#define MAR132 (int *) 0x01848210
/* CONTROL EMIFA CE0 RANGE 85000000H~85FFFFFFH */
#define MAR133 (int *) 0x01848214
/* CONTROL EMIFA CE0 RANGE 86000000H~86FFFFFFH */
#define MAR134 (int *) 0x01848218
/* CONTROL EMIFA CE0 RANGE 87000000H~87FFFFFFH */
#define MAR135 (int *) 0x0184821c
/* CONTROL EMIFA CE0 RANGE 88000000H~88FFFFFFH */
#define MAR136 (int *) 0x01848220
/* CONTROL EMIFA CE0 RANGE 89000000H~89FFFFFFH */
#define MAR137 (int *) 0x01848224
/* CONTROL EMIFA CE0 RANGE 8A000000H~8AFFFFFFH */
#define MAR138 (int *) 0x01848228
/* CONTROL EMIFA CE0 RANGE 8B000000H~8BFFFFFFH */
#define MAR139 (int *) 0x0184822c
/* CONTROL EMIFA CE0 RANGE 8c000000H~8cFFFFFFH */
#define MAR140 (int *) 0x01848230
/* CONTROL EMIFA CE0 RANGE 8d000000H~8dFFFFFFH */
#define MAR141 (int *) 0x01848234
/* CONTROL EMIFA CE0 RANGE 8e000000H~8eFFFFFFH */
#define MAR142 (int *) 0x01848238
/* CONTROL EMIFA CE0 RANGE 8f000000H~8fFFFFFFH */
#define MAR143 (int *) 0x0184823c

/* CONTROL EMIFA CE1 RANGE 90000000H~90FFFFFFH */
#define MAR144 (int *) 0x01848240
/* CONTROL EMIFA CE1 RANGE 91000000H~91FFFFFFH */
#define MAR145 (int *) 0x01848244
/* CONTROL EMIFA CE1 RANGE 92000000H~92FFFFFFH */
#define MAR146 (int *) 0x01848248
/* CONTROL EMIFA CE1 RANGE 93000000H~93FFFFFFH */
#define MAR147 (int *) 0x0184824c
/* CONTROL EMIFA CE1 RANGE 94000000H~94FFFFFFH */
#define MAR148 (int *) 0x01848250
/* CONTROL EMIFA CE1 RANGE 95000000H~95FFFFFFH */
#define MAR149 (int *) 0x01848254
/* CONTROL EMIFA CE1 RANGE 96000000H~96FFFFFFH */
#define MAR150 (int *) 0x01848258
/* CONTROL EMIFA CE1 RANGE 97000000H~97FFFFFFH */
#define MAR151 (int *) 0x0184825c
/* CONTROL EMIFA CE1 RANGE 98000000H~98FFFFFFH */
#define MAR152 (int *) 0x01848260
/* CONTROL EMIFA CE1 RANGE 99000000H~99FFFFFFH */
#define MAR153 (int *) 0x01848264
/* CONTROL EMIFA CE1 RANGE 9A000000H~9AFFFFFFH */
#define MAR154 (int *) 0x01848268
/* CONTROL EMIFA CE1 RANGE 9B000000H~9BFFFFFFH */
#define MAR155 (int *) 0x0184826c
/* CONTROL EMIFA CE1 RANGE 9C000000H~9CFFFFFFH */
#define MAR156 (int *) 0x01848270
/* CONTROL EMIFA CE1 RANGE 9D000000H~9DFFFFFFH */
#define MAR157 (int *) 0x01848274
/* CONTROL EMIFA CE1 RANGE 9E000000H~9EFFFFFFH */
#define MAR158 (int *) 0x01848278
/* CONTROL EMIFA CE1 RANGE 9F000000H~9FFFFFFFH */
#define MAR159 (int *) 0x0184827c

/* CONTROL EMIFA CE2 RANGE a0000000H~a0FFFFFFH */
#define MAR160 (int *) 0x01848280
/* CONTROL EMIFA CE2 RANGE a1000000H~a1FFFFFFH */
#define MAR161 (int *) 0x01848284
/* CONTROL EMIFA CE2 RANGE a2000000H~a2FFFFFFH */
#define MAR162 (int *) 0x01848288
/* CONTROL EMIFA CE2 RANGE a3000000H~a3FFFFFFH */
#define MAR163 (int *) 0x0184828c
/* CONTROL EMIFA CE2 RANGE a4000000H~a4FFFFFFH */
#define MAR164 (int *) 0x01848290
/* CONTROL EMIFA CE2 RANGE a5000000H~a5FFFFFFH */
#define MAR165 (int *) 0x01848294
/* CONTROL EMIFA CE2 RANGE a6000000H~a6FFFFFFH */
#define MAR166 (int *) 0x01848298
/* CONTROL EMIFA CE2 RANGE a7000000H~a7FFFFFFH */
#define MAR167 (int *) 0x0184829c
/* CONTROL EMIFA CE2 RANGE a8000000H~a8FFFFFFH */
#define MAR168 (int *) 0x018482a0
/* CONTROL EMIFA CE2 RANGE a9000000H~a9FFFFFFH */
#define MAR169 (int *) 0x018482a4
/* CONTROL EMIFA CE2 RANGE aa000000H~aaFFFFFFH */
#define MAR170 (int *) 0x018482a8
/* CONTROL EMIFA CE2 RANGE ab000000H~abFFFFFFH */
#define MAR171 (int *) 0x018482ac
/* CONTROL EMIFA CE2 RANGE ac000000H~acFFFFFFH */
#define MAR172 (int *) 0x018482b0
/* CONTROL EMIFA CE2 RANGE ad000000H~adFFFFFFH */
#define MAR173 (int *) 0x018482b4
/* CONTROL EMIFA CE2 RANGE ae000000H~aeFFFFFFH */
#define MAR174 (int *) 0x018482b8
/* CONTROL EMIFA CE2 RANGE af000000H~afFFFFFFH */
#define MAR175 (int *) 0x018482bc

/* CONTROL EMIFA CE3 RANGE b0000000H~b0FFFFFFH */
#define MAR176 (int *) 0x018482c0
/* CONTROL EMIFA CE3 RANGE b1000000H~b1FFFFFFH */
#define MAR177 (int *) 0x018482c4
/* CONTROL EMIFA CE3 RANGE b2000000H~b2FFFFFFH */
#define MAR178 (int *) 0x018482c8
/* CONTROL EMIFA CE3 RANGE b3000000H~b3FFFFFFH */
#define MAR179 (int *) 0x018482cc
/* CONTROL EMIFA CE3 RANGE b4000000H~b4FFFFFFH */
#define MAR180 (int *) 0x018482d0
/* CONTROL EMIFA CE3 RANGE b5000000H~b5FFFFFFH */
#define MAR181 (int *) 0x018482d4
/* CONTROL EMIFA CE3 RANGE b6000000H~b6FFFFFFH */
#define MAR182 (int *) 0x018482d8
/* CONTROL EMIFA CE3 RANGE b7000000H~b7FFFFFFH */
#define MAR183 (int *) 0x018482dc
/* CONTROL EMIFA CE3 RANGE b8000000H~b8FFFFFFH */
#define MAR184 (int *) 0x018482e0
/* CONTROL EMIFA CE3 RANGE b9000000H~b9FFFFFFH */
#define MAR185 (int *) 0x018482e4
/* CONTROL EMIFA CE3 RANGE ba000000H~baFFFFFFH */
#define MAR186 (int *) 0x018482e8
/* CONTROL EMIFA CE3 RANGE bb000000H~bbFFFFFFH */
#define MAR187 (int *) 0x018482ec
/* CONTROL EMIFA CE3 RANGE bc000000H~bcFFFFFFH */
#define MAR188 (int *) 0x018482f0
/* CONTROL EMIFA CE3 RANGE bd000000H~bdFFFFFFH */
#define MAR189 (int *) 0x018482f4
/* CONTROL EMIFA CE3 RANGE be000000H~beFFFFFFH */
#define MAR190 (int *) 0x018482f8
/* CONTROL EMIFA CE3 RANGE bf000000H~bfFFFFFFH */
#define MAR191 (int *) 0x018482fc

/* EMIFA MEMORY-MAPPED REGISTERS */

/* EMIFA GLOBAL CONTROL */
#define GBLCTLA (int *) 0x01800000
/* EMIFA CE1 SPACE CONTROL */
#define CE1CTLA (int *) 0x01800004
/* EMIFA CE0 SPACE CONTROL */
#define CE0CTLA (int *) 0x01800008
/* EMIFA CE2 SPACE CONTROL */
#define CE2CTLA (int *) 0x01800010
/* EMIFA CE3 SPACE CONTROL */
#define CE3CTLA (int *) 0x01800014
/* EMIFA SDRAM CONTROL */
#define SDCTLA (int *) 0x01800018
/* EMIFA SDTIM REFRESH CONTROL */
#define SDTIMA (int *) 0x0180001C
/* EMIFA SDRAM EXTENTION */
#define SDEXTA (int *) 0x01800020
/* EMIFA CE1 SPACE SECONDARY CONTROL */
#define CE1SECA (int *) 0x01800044
/* EMIFA CE1 SPACE SECONDARY CONTROL */
#define CE0SECA (int *) 0x01800048
/* EMIFA CE1 SPACE SECONDARY CONTROL */
#define CE2SECA (int *) 0x01800050
/* EMIFA CE1 SPACE SECONDARY CONTROL */
#define CE3SECA (int *) 0x01800054

/* EMIFB GLOBAL CONTROL */
#define GBLCTLB (volatile unsigned int *) 0x01A80000
/* EMIFB CE1 SPACE CONTROL */
#define CE1CTLB (volatile unsigned int *) 0x01A80004
/* EMIFB CE0 SPACE CONTROL */
#define CE0CTLB (volatile unsigned int *) 0x01A80008
/* EMIFB CE2 SPACE CONTROL */
#define CE2CTLB (volatile unsigned int *) 0x01A80010
/* EMIFB CE3 SPACE CONTROL */
#define CE3CTLB (volatile unsigned int *) 0x01A80014
/* EMIFB SDRAM CONTROL */
#define SDCTLB (volatile unsigned int *) 0x01A80018
/* EMIFB SDTIM REFRESH CONTROL */
#define SDTIMB (volatile unsigned int *) 0x01A8001C
/* EMIFB SDRAM EXTENTION */
#define SDEXTB (volatile unsigned int *) 0x01A80020
/* EMIFB CE1 SPACE SECONDARY CONTROL */
#define CE1SECB (volatile unsigned int *) 0x01A80044
/* EMIFB CE1 SPACE SECONDARY CONTROL */
#define CE0SECB (volatile unsigned int *) 0x01A80048
/* EMIFB CE1 SPACE SECONDARY CONTROL */
#define CE2SECB (volatile unsigned int *) 0x01A80050
/* EMIFB CE1 SPACE SECONDARY CONTROL */
#define CE3SECB (volatile unsigned int *) 0x01A80054

/* TIMER REGISTERS */

/* TIMER 0 CONTROL REGISTER */
#define CTL0 (volatile unsigned int *) 0x01940000
/* TIMER 0 PERIOD REGISTER */
#define PRD0 (volatile unsigned int *) 0x01940004
/* TIMER 0 COUNTER REGISTER */
#define CNT0 (volatile unsigned int *) 0x01940008

/* TIMER 1 CONTROL REGISTER */
#define CTL1 (volatile unsigned int *) 0x01980000
/* TIMER 1 PERIOD REGISTER */
#define PRD1 (volatile unsigned int *) 0x01980004
/* TIMER 1 COUNTER REGISTER */
#define CNT1 (volatile unsigned int *) 0x01980008

/* TIMER 2 CONTROL REGISTER */
#define CTL2 (volatile unsigned int *) 0x01AC0000
/* TIMER 2 PERIOD REGISTER */
#define PRD2 (volatile unsigned int *) 0x01AC0004
/* TIMER 2 COUNTER REGISTER */
#define CNT2 (volatile unsigned int *) 0x01AC0008

/* INTERRUPT SELECTOR REGISTERS */
/* INTERRUPT MULTIPLEXER HIGH */
#define MUXH (volatile unsigned int *) 0x019C0000
/* INTERRUPT MULTIPLEXER LOW */
#define MUXL (volatile unsigned int *) 0x019C0004
/* EXTERNAL INTERRUPT POLARITY */
#define EXTPOL (volatile unsigned int *) 0x019C0008

/* */
#define IFR (volatile unsigned int *)0x400;

#endif