?? csl_dat_.sa
字號:
********************************************************************************
* Copyright (C) 1999-2000 Texas Instruments Incorporated.
* All Rights Reserved
*------------------------------------------------------------------------------
* FILENAME...... csl_dat_.sa
* DATE CREATED.. 11/11/1999
* LAST MODIFIED. 10/03/2000
********************************************************************************
.include "csl_chiphal.inc"
.global _DAT_wait
.global _DAT_busy
.global _DAT_fill
.global _DAT_copy
.global _DAT_copy2d
.ref __DAT_serialTable
.ref __DAT_stateStruct
.if DAT_SUPPORT
.if DMA_SUPPORT
********************************************************************************
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
* DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT DMA_SUPPORT
********************************************************************************
;DMA register offsets
PRICTL .set 0
SECCTL .set 2
SRC .set 4
DST .set 6
XFRCNT .set 8
;State structure, must match that in the C file
State .struct
useMask .word
baseAddr .word
gblcntAddr .word
gblidxAddr .word
initPrictl .word
.endstruct
*------------------------------------------------------------------------------*
* void DAT_wait(Uint32 id);
*------------------------------------------------------------------------------*
_DAT_wait .cproc id
.reg gieSave
.reg X
.reg slotNumber
.reg serialNumber
.reg tableAddr
.reg oldSerialNumber
.reg pred
.reg mask
.reg irfReg
.reg stateAddr
.reg useMask
;first let's check to see if this is the magic wait-for-all ID
CMPEQ id,-1,pred
[!pred] B DAT_WAIT_NORMAL
;at this point, the ID is the wait-for-all magic id
;this means we have to wait for ALL tranfers to complete
;Load useMask
MVKL __DAT_stateStruct,stateAddr
MVKH __DAT_stateStruct,stateAddr
LDW *stateAddr(State.useMask),useMask
DAT_WAIT_LOOP0:
;Wait until all mask bits appears in the IFR
MVC IFR,irfReg
AND useMask,irfReg,X
CMPEQ useMask,X,pred
[!pred] B DAT_WAIT_LOOP0
B DAT_WAIT_RETURN
DAT_WAIT_NORMAL:
;Extract slot number and serial number from id
MVKL 0x000000FF,X
MVKH 0x000000FF,X
AND id,X,slotNumber
SHRU id,16,serialNumber
;Load old serial number from table
MVKL __DAT_serialTable,tableAddr
MVKH __DAT_serialTable,tableAddr
LDHU *tableAddr[slotNumber],oldSerialNumber
;If the serial numbers don't match then return
CMPEQ serialNumber,oldSerialNumber,pred
[!pred] B DAT_WAIT_RETURN
;Generate IFR mask from slot number (mask = 1<<slotNumber)
MVK 1,mask
SHL mask,slotNumber,mask
DAT_WAIT_LOOP1:
;Wait until the mask bit appears in the IFR
MVC IFR,irfReg
AND mask,irfReg,pred
[!pred] B DAT_WAIT_LOOP1
DAT_WAIT_RETURN:
.return
.endproc
*------------------------------------------------------------------------------*
* int DAT_busy(Uint32 id);
*------------------------------------------------------------------------------*
_DAT_busy .cproc id
.reg gieSave
.reg X
.reg slotNumber
.reg serialNumber
.reg tableAddr
.reg oldSerialNumber
.reg pred
.reg mask
.reg irfReg
.reg busyFlag
;set busy flag to zero
ZERO busyFlag
;Extract slot number and serial number from id
MVKL 0x000000FF,X
MVKH 0x000000FF,X
AND id,X,slotNumber
SHRU id,16,serialNumber
;Load old serial number from table
MVKL __DAT_serialTable,tableAddr
MVKH __DAT_serialTable,tableAddr
LDHU *tableAddr[slotNumber],oldSerialNumber
;If the serial numbers don't match then return
CMPEQ serialNumber,oldSerialNumber,pred
[!pred] B DAT_BUSY_RETURN
;Generate IFR mask from slot number (mask = 1<<slotNumber)
MVK 1,mask
SHL mask,slotNumber,mask
;check to see if the mask bit appears in the IFR
MVC IFR,irfReg
AND mask,irfReg,pred
[pred] B DAT_BUSY_RETURN
;the IFR flag was not set, hence the slot IS busy
ADD busyFlag,1,busyFlag
DAT_BUSY_RETURN:
.return busyFlag
.endproc
*------------------------------------------------------------------------------*
* Uint32 DAT_fill(void *dst , Uint16 byteCnt, Uint32 *value);
*------------------------------------------------------------------------------*
_DAT_fill .cproc dst, byteCnt, value
.reg gieSave
.reg X,Y
.reg const31
.reg stateAddr
.reg useMask
.reg slotNumber
.reg serialNumber
.reg tableAddr
.reg oldSerialNumber
.reg pred
.reg mask
.reg irfReg
.reg id
.reg alignment
.reg dmaBase
.reg initPrictl
;Load useMask and Initial primary control register
MVKL __DAT_stateStruct,stateAddr
MVKH __DAT_stateStruct,stateAddr
LDW *stateAddr(State.useMask),useMask
LDW *stateAddr(State.initPrictl),initPrictl
;Constant needed later
MVK 31,const31
DAT_FILL_LOOP1:
;Wait for a free slot to open up
MVC IFR,irfReg
AND irfReg,useMask,X
LMBD 1,X,X
SUB const31,X,slotNumber
CMPEQ slotNumber,-1,pred
[pred] B DAT_FILL_LOOP1
;Save and clear GIE
MVC CSR,X
AND X,1,gieSave
AND X,-2,X
MVC X,CSR
;Generate mask from slot number
MVK 1,mask
SHL mask,slotNumber,mask
;Clear interrupt pending flag
MVC mask,ICR
;Load up serial number table address
MVKL __DAT_serialTable,tableAddr
MVKH __DAT_serialTable,tableAddr
LDHU *tableAddr[slotNumber],oldSerialNumber
;Add one to serial numer and store it back into the table
ADD oldSerialNumber,1,serialNumber
STH serialNumber,*tableAddr[slotNumber]
;Construct transfer id from serial number and slot number
SHL serialNumber,16,id
OR id,slotNumber,id
;Load up base address of DMA registers
LDW *stateAddr(State.baseAddr),dmaBase
;Store zero into DMA primary control register
MVKL 0x00000000,X
MVKH 0x00000000,X
STW X,*dmaBase[PRICTL]
;Store source address
STW value,*dmaBase[SRC]
;Store destination address
STW dst,*dmaBase[DST]
;Store secondary control register
MVKL 0x0000A080,Y
MVKH 0x0000A080,Y
STW Y,*dmaBase[SECCTL]
;Calculate argument alignment
OR dst,byteCnt,alignment
OR value,alignment,alignment
AND alignment,3,alignment
DAT_FILL_32:
;Check to see if 32-bit aligned, branch if not
CMPEQ alignment,0,pred
[!pred] B DAT_FILL_16
;Store transfer count
SHRU byteCnt,2,X
STW X,*dmaBase[XFRCNT]
;Store primary control register
MVKL 0x00000041,Y
MVKH 0x00000041,Y
OR Y,initPrictl,Y
STW Y,*dmaBase[PRICTL]
;All done so go to procedure exit code
B DAT_FILL_RETURN
DAT_FILL_16:
;Check to see if 16-bit aligned, branch if not
CMPEQ alignment,2,pred
[!pred] B DAT_FILL_8
;Store transfer count
SHRU byteCnt,1,X
STW X,*dmaBase[XFRCNT]
;Store primary control register
MVKL 0x00000141,Y
MVKH 0x00000141,Y
OR Y,initPrictl,Y
STW Y,*dmaBase[PRICTL]
;All done so go to procedure exit code
B DAT_FILL_RETURN
DAT_FILL_8:
;Must be 8-bit aligned since it wasn't 32 or 16 bit aligned
;Store transfer count
STW byteCnt,*dmaBase[XFRCNT]
;Store primary control register
MVKL 0x00000241,Y
MVKH 0x00000241,Y
OR Y,initPrictl,Y
STW Y,*dmaBase[PRICTL]
DAT_FILL_RETURN:
;Restore GIE
MVC CSR,X
OR X,gieSave,X
MVC X,CSR
.return id
.endproc
*------------------------------------------------------------------------------*
* Uint32 DAT_copy(void *src , void *dst , Uint16 byteCnt);
*------------------------------------------------------------------------------*
_DAT_copy .cproc src, dst, byteCnt
.reg gieSave
.reg X,Y
.reg const31
.reg stateAddr
.reg useMask
.reg slotNumber
.reg serialNumber
.reg tableAddr
.reg oldSerialNumber
.reg pred
.reg mask
.reg irfReg
.reg id
.reg alignment
.reg dmaBase
.reg initPrictl
;Load useMask and Initial primary control register
MVKL __DAT_stateStruct,stateAddr
MVKH __DAT_stateStruct,stateAddr
LDW *stateAddr(State.useMask),useMask
LDW *stateAddr(State.initPrictl),initPrictl
;Constant needed later
MVK 31,const31
DAT_COPY_LOOP1:
;Wait for a free slot to open up
MVC IFR,irfReg
AND irfReg,useMask,X
LMBD 1,X,X
SUB const31,X,slotNumber
CMPEQ slotNumber,-1,pred
[pred] B DAT_COPY_LOOP1
;Save and clear GIE
MVC CSR,X
AND X,1,gieSave
AND X,-2,X
MVC X,CSR
;Generate mask from slot number
MVK 1,mask
SHL mask,slotNumber,mask
;Clear interrupt pending flag
MVC mask,ICR
;Load up serial number table address
MVKL __DAT_serialTable,tableAddr
MVKH __DAT_serialTable,tableAddr
LDHU *tableAddr[slotNumber],oldSerialNumber
;Add one to serial numer and store it back into the table
ADD oldSerialNumber,1,serialNumber
STH serialNumber,*tableAddr[slotNumber]
;Construct transfer id from serial number and slot number
SHL serialNumber,16,id
OR id,slotNumber,id
;Load up base address of DMA registers
LDW *stateAddr(State.baseAddr),dmaBase
;Store zero into DMA primary control register
MVKL 0x00000000,X
MVKH 0x00000000,X
STW X,*dmaBase[PRICTL]
;Store source address
STW src,*dmaBase[SRC]
;Store destination address
STW dst,*dmaBase[DST]
;Store secondary control register
MVKL 0x0000A080,Y
MVKH 0x0000A080,Y
STW Y,*dmaBase[SECCTL]
;Calculate argument alignment
OR src,dst,alignment
OR byteCnt,alignment,alignment
AND alignment,3,alignment
DAT_COPY_32:
;Check to see if 32-bit aligned, branch if not
CMPEQ alignment,0,pred
[!pred] B DAT_COPY_16
;Store transfer count
SHRU byteCnt,2,X
STW X,*dmaBase[XFRCNT]
;Store primary control register
MVKL 0x00000051,Y
MVKH 0x00000051,Y
OR Y,initPrictl,Y
STW Y,*dmaBase[PRICTL]
;All done so go to procedure exit code
B DAT_COPY_RETURN
DAT_COPY_16:
;Check to see if 16-bit aligned, branch if not
CMPEQ alignment,2,pred
[!pred] B DAT_COPY_8
;Store transfer count
SHRU byteCnt,1,X
STW X,*dmaBase[XFRCNT]
;Store primary control register
MVKL 0x00000151,Y
MVKH 0x00000151,Y
OR Y,initPrictl,Y
STW Y,*dmaBase[PRICTL]
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