/******************************************************************************\*           Copyright (C) 1999-2000 Texas Instruments Incorporated.*                           All Rights Reserved*------------------------------------------------------------------------------* FILENAME...... csl_emifhal.h* DATE CREATED.. 06/12/1999 * LAST MODIFIED. 06/17/2003  Added CHIP_6712C*                05/28/2003  Added CHIP_6711C*                10/03/2000*------------------------------------------------------------------------------* REGISTERS** GBLCTL  - global control register* CECTL0  - CE space control register 0* CECTL1  - CE space control register 1* CECTL2  - CE space control register 2* CECTL3  - CE space control register 3* SDCTL   - SDRAM control regsiter* SDTIM   - SDRAM timing register* SDEXT   - SDRAM extension register (1)** (1) - only supported on 6211,6711,6712,6713,6711C,6712C* \******************************************************************************/#ifndef _CSL_EMIFHAL_H_#define _CSL_EMIFHAL_H_#include <csl_stdinc.h>#include <csl_chip.h>#if (EMIF_SUPPORT)/******************************************************************************\* MISC section\******************************************************************************/#define _EMIF_BASE_GLOBAL   0x01800000u/******************************************************************************\* module level register/field access macros\******************************************************************************/  /* ----------------- */  /* FIELD MAKE MACROS */  /* ----------------- */  #define EMIF_FMK(REG,FIELD,x)\    _PER_FMK(EMIF,##REG,##FIELD,x)  #define EMIF_FMKS(REG,FIELD,SYM)\    _PER_FMKS(EMIF,##REG,##FIELD,##SYM)    /* -------------------------------- */  /* RAW REGISTER/FIELD ACCESS MACROS */  /* -------------------------------- */  #define EMIF_ADDR(REG)\    _EMIF_##REG##_ADDR  #define EMIF_RGET(REG)\    _PER_RGET(_EMIF_##REG##_ADDR,EMIF,##REG)  #define EMIF_RSET(REG,x)\    _PER_RSET(_EMIF_##REG##_ADDR,EMIF,##REG,x)  #define EMIF_FGET(REG,FIELD)\    _EMIF_##REG##_FGET(##FIELD)  #define EMIF_FSET(REG,FIELD,x)\    _EMIF_##REG##_FSET(##FIELD,##x)  #define EMIF_FSETS(REG,FIELD,SYM)\    _EMIF_##REG##_FSETS(##FIELD,##SYM)    /* ------------------------------------------ */  /* ADDRESS BASED REGISTER/FIELD ACCESS MACROS */  /* ------------------------------------------ */  #define EMIF_RGETA(addr,REG)\    _PER_RGET(addr,EMIF,##REG)  #define EMIF_RSETA(addr,REG,x)\    _PER_RSET(addr,EMIF,##REG,x)  #define EMIF_FGETA(addr,REG,FIELD)\    _PER_FGET(addr,EMIF,##REG,##FIELD)  #define EMIF_FSETA(addr,REG,FIELD,x)\    _PER_FSET(addr,EMIF,##REG,##FIELD,x)  #define EMIF_FSETSA(addr,REG,FIELD,SYM)\    _PER_FSETS(addr,EMIF,##REG,##FIELD,##SYM)/******************************************************************************\* _____________________* |                   |* |  G B L C T L      |* |___________________|** GBLCTL  - global control register** FIELDS (msb -> lsb)* (r)  BUSREQ  (1)* (r)  ARDY* (r)  HOLD* (r)  HOLDA* (rw) NOHOLD* (rw) SDCEN   (2)* (rw) SSCEN   (2)* (rw) EKEN    (4)* (rw) CLK1EN* (rw) CLK2EN  (3)* (rw) SSCRT   (2)(3)* (rw) RBTR8   (2)* (r)  MAP     (2)** (1) - Field only exists for C11_SUPPORT* (2) - Field does not exist for C11_SUPPORT* (3) - Field does not exist for 6202/6203/6204/6205 * (4) - Field only exixts for C6713, DA610, 6711C, 6712C*\******************************************************************************/  #define _EMIF_GBLCTL_OFFSET          0  #define _EMIF_GBLCTL_ADDR            0x01800000u#if (C11_SUPPORT)  #define _EMIF_GBLCTL_BUSREQ_MASK     0x00000800u  #define _EMIF_GBLCTL_BUSREQ_SHIFT    0x0000000Bu  #define  EMIF_GBLCTL_BUSREQ_DEFAULT  0x00000000u  #define  EMIF_GBLCTL_BUSREQ_OF(x)    _VALUEOF(x)  #define  EMIF_GBLCTL_BUSREQ_LOW      0x00000000u  #define  EMIF_GBLCTL_BUSREQ_HIGH     0x00000001u#endif  #define _EMIF_GBLCTL_ARDY_MASK       0x00000400u  #define _EMIF_GBLCTL_ARDY_SHIFT      0x0000000Au  #define  EMIF_GBLCTL_ARDY_DEFAULT    0x00000000u  #define  EMIF_GBLCTL_ARDY_OF(x)      _VALUEOF(x)  #define  EMIF_GBLCTL_ARDY_LOW        0x00000000u  #define  EMIF_GBLCTL_ARDY_HIGH       0x00000001u  #define _EMIF_GBLCTL_HOLD_MASK       0x00000200u  #define _EMIF_GBLCTL_HOLD_SHIFT      0x00000009u  #define  EMIF_GBLCTL_HOLD_DEFAULT    0x00000000u  #define  EMIF_GBLCTL_HOLD_OF(x)      _VALUEOF(x)  #define  EMIF_GBLCTL_HOLD_LOW        0x00000000u  #define  EMIF_GBLCTL_HOLD_HIGH       0x00000001u  #define _EMIF_GBLCTL_HOLDA_MASK      0x00000100u  #define _EMIF_GBLCTL_HOLDA_SHIFT     0x00000008u  #define  EMIF_GBLCTL_HOLDA_DEFAULT   0x00000000u  #define  EMIF_GBLCTL_HOLDA_OF(x)     _VALUEOF(x)  #define  EMIF_GBLCTL_HOLDA_LOW       0x00000000u  #define  EMIF_GBLCTL_HOLDA_HIGH      0x00000001u  #define _EMIF_GBLCTL_NOHOLD_MASK     0x00000080u  #define _EMIF_GBLCTL_NOHOLD_SHIFT    0x00000007u  #define  EMIF_GBLCTL_NOHOLD_DEFAULT  0x00000000u  #define  EMIF_GBLCTL_NOHOLD_OF(x)    _VALUEOF(x)  #define  EMIF_GBLCTL_NOHOLD_DISABLE  0x00000000u  #define  EMIF_GBLCTL_NOHOLD_ENABLE   0x00000001u#if (CHIP_6201 | CHIP_6202 | CHIP_6203 | CHIP_6204 | CHIP_6205 | CHIP_6701)  #define _EMIF_GBLCTL_SDCEN_MASK      0x00000040u  #define _EMIF_GBLCTL_SDCEN_SHIFT     0x00000006u  #define  EMIF_GBLCTL_SDCEN_DEFAULT   0x00000001u  #define  EMIF_GBLCTL_SDCEN_OF(x)     _VALUEOF(x)  #define  EMIF_GBLCTL_SDCEN_DISABLE   0x00000000u  #define  EMIF_GBLCTL_SDCEN_ENABLE    0x00000001u#endif#if (CHIP_6201 | CHIP_6202 | CHIP_6203 | CHIP_6204 | CHIP_6205 | CHIP_6701)  #define _EMIF_GBLCTL_SSCEN_MASK      0x00000020u  #define _EMIF_GBLCTL_SSCEN_SHIFT     0x00000005u  #define  EMIF_GBLCTL_SSCEN_DEFAULT   0x00000001u  #define  EMIF_GBLCTL_SSCEN_OF(x)     _VALUEOF(x)  #define  EMIF_GBLCTL_SSCEN_DISABLE   0x00000000u  #define  EMIF_GBLCTL_SSCEN_ENABLE    0x00000001u#endif#if (CHIP_6713 || CHIP_DA610 || CHIP_6711C || CHIP_6712C)  #define _EMIF_GBLCTL_EKEN_MASK       0x00000020u  #define _EMIF_GBLCTL_EKEN_SHIFT      0x00000005u  #define  EMIF_GBLCTL_EKEN_DEFAULT    0x00000001u  #define  EMIF_GBLCTL_EKEN_OF(x)      _VALUEOF(x)  #define  EMIF_GBLCTL_EKEN_DISABLE    0x00000000u  #define  EMIF_GBLCTL_EKEN_ENABLE     0x00000001u#endif  #define _EMIF_GBLCTL_CLK1EN_MASK     0x00000010u  #define _EMIF_GBLCTL_CLK1EN_SHIFT    0x00000004u#if (CHIP_6713 || CHIP_DA610)  #define  EMIF_GBLCTL_CLK1EN_DEFAULT  0x00000000u#else  #define  EMIF_GBLCTL_CLK1EN_DEFAULT  0x00000001u#endif  #define  EMIF_GBLCTL_CLK1EN_OF(x)    _VALUEOF(x)  #define  EMIF_GBLCTL_CLK1EN_DISABLE  0x00000000u  #define  EMIF_GBLCTL_CLK1EN_ENABLE   0x00000001u#if (!(CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205))  #define _EMIF_GBLCTL_CLK2EN_MASK     0x00000008u  #define _EMIF_GBLCTL_CLK2EN_SHIFT    0x00000003u  #define  EMIF_GBLCTL_CLK2EN_DEFAULT  0x00000001u  #define  EMIF_GBLCTL_CLK2EN_OF(x)    _VALUEOF(x)  #define  EMIF_GBLCTL_CLK2EN_DISABLE  0x00000000u  #define  EMIF_GBLCTL_CLK2EN_ENABLE   0x00000001u#endif#if (CHIP_6201|CHIP_6701)  #define _EMIF_GBLCTL_SSCRT_MASK      0x00000004u  #define _EMIF_GBLCTL_SSCRT_SHIFT     0x00000002u  #define  EMIF_GBLCTL_SSCRT_DEFAULT   0x00000000u  #define  EMIF_GBLCTL_SSCRT_OF(x)     _VALUEOF(x)  #define  EMIF_GBLCTL_SSCRT_CPUOVR2   0x00000000u  #define  EMIF_GBLCTL_SSCRT_CPU       0x00000001u#endif#if (!C11_SUPPORT)  #define _EMIF_GBLCTL_RBTR8_MASK      0x00000002u  #define _EMIF_GBLCTL_RBTR8_SHIFT     0x00000001u  #define  EMIF_GBLCTL_RBTR8_DEFAULT   0x00000000u  #define  EMIF_GBLCTL_RBTR8_OF(x)     _VALUEOF(x)  #define  EMIF_GBLCTL_RBTR8_HPRI      0x00000000u  #define  EMIF_GBLCTL_RBTR8_8ACC      0x00000001u#endif#if (!C11_SUPPORT)  #define _EMIF_GBLCTL_MAP_MASK        0x00000001u  #define _EMIF_GBLCTL_MAP_SHIFT       0x00000000u  #define  EMIF_GBLCTL_MAP_MAP1        0x00000000u  #define  EMIF_GBLCTL_MAP_MAP0        0x00000001u  #define  EMIF_GBLCTL_MAP_DEFAULT     0x00000000u  #define  EMIF_GBLCTL_MAP_OF(x)       _VALUEOF(x)#endif  #define  EMIF_GBLCTL_OF(x)           _VALUEOF(x)#if (CHIP_6201|CHIP_6701)  #define EMIF_GBLCTL_DEFAULT (Uint32)( \    0x00003000\    |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\    |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\    |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\    |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\    |_PER_FDEFAULT(EMIF,GBLCTL,SDCEN)\    |_PER_FDEFAULT(EMIF,GBLCTL,SSCEN)\    |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\    |_PER_FDEFAULT(EMIF,GBLCTL,CLK2EN)\    |_PER_FDEFAULT(EMIF,GBLCTL,SSCRT)\    |_PER_FDEFAULT(EMIF,GBLCTL,RBTR8)\    |_PER_FDEFAULT(EMIF,GBLCTL,MAP)\  )  #define EMIF_GBLCTL_RMK(nohold,sdcen,sscen,clk1en,clk2en,sscrt,rbtr8) \    (Uint32)( \     _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\    |_PER_FMK(EMIF,GBLCTL,SDCEN,sdcen)\    |_PER_FMK(EMIF,GBLCTL,SSCEN,sscen)\    |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\    |_PER_FMK(EMIF,GBLCTL,CLK2EN,clk2en)\    |_PER_FMK(EMIF,GBLCTL,SSCRT,sscrt)\    |_PER_FMK(EMIF,GBLCTL,RBTR8,rbtr8)\  )#endif#if (CHIP_6211|CHIP_6711)  #define EMIF_GBLCTL_DEFAULT (Uint32)( \    0x00003000\    |_PER_FDEFAULT(EMIF,GBLCTL,BUSREQ)\    |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\    |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\    |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\    |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\    |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\    |_PER_FDEFAULT(EMIF,GBLCTL,CLK2EN)\  )  #define EMIF_GBLCTL_RMK(nohold,clk1en,clk2en) (Uint32)( \     _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\    |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\    |_PER_FMK(EMIF,GBLCTL,CLK2EN,clk2en)\  )#endif#if (CHIP_6202|CHIP_6203|CHIP_6204|CHIP_6205)  #define EMIF_GBLCTL_DEFAULT (Uint32)( \    0x00003008\    |_PER_FDEFAULT(EMIF,GBLCTL,ARDY)\    |_PER_FDEFAULT(EMIF,GBLCTL,HOLD)\    |_PER_FDEFAULT(EMIF,GBLCTL,HOLDA)\    |_PER_FDEFAULT(EMIF,GBLCTL,NOHOLD)\    |_PER_FDEFAULT(EMIF,GBLCTL,SDCEN)\    |_PER_FDEFAULT(EMIF,GBLCTL,SSCEN)\    |_PER_FDEFAULT(EMIF,GBLCTL,CLK1EN)\    |_PER_FDEFAULT(EMIF,GBLCTL,RBTR8)\    |_PER_FDEFAULT(EMIF,GBLCTL,MAP)\  )  #define EMIF_GBLCTL_RMK(nohold,sdcen,sscen,clk1en,rbtr8) (Uint32)( \     _PER_FMK(EMIF,GBLCTL,NOHOLD,nohold)\    |_PER_FMK(EMIF,GBLCTL,SDCEN,sdcen)\    |_PER_FMK(EMIF,GBLCTL,SSCEN,sscen)\    |_PER_FMK(EMIF,GBLCTL,CLK1EN,clk1en)\