IDEF void VP_configPort(VP_Handle hVp, VP_ConfigPort *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x0,x1,x2;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x0  =  config->vpctl;  x1  =  config->vpie;  x2  =  config->vpis;  base[_VP_VPCTL_OFFSET]  =  x0;  base[_VP_VPIE_OFFSET]   =  x1;  base[_VP_VPIS_OFFSET]   =  x2;  IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*/IDEF void VP_configCapture(VP_Handle hVp, VP_ConfigCapture *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19;  register int x20,x21,x22,x23,x24,x25,x26;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x3  =  config->vcastrt1;   x4  =  config->vcastop1;   x5  =  config->vcastrt2;   x6  =  config->vcastop2;   x7  =  config->vcavint;   x8  =  config->vcathrld;   x9  =  config->vcaevtct;   x10 =  config->vcbstrt1;   x11 =  config->vcbstop1;   x12 =  config->vcbstrt2;   x13 =  config->vcbstop2;   x14 =  config->vcbvint;   x15 =  config->vcbthrld;   x16 =  config->vcbevtct;   x17 =  config->tsictl;   x18 =  config->tsiclkinitl;   x19 =  config->tsiclkinitm;  x20 =  config->tsistcmpl;   x21 =  config->tsistcmpm;  x22 =  config->tsistmskl;   x23 =  config->tsistmskm;  x24 =  config->tsiticks;   x25 =  config->vcactl;   x26 =  config->vcbctl;   base[_VP_VCASTRT1_OFFSET]    =    x3;  base[_VP_VCASTOP1_OFFSET]    =    x4;    base[_VP_VCASTRT2_OFFSET]    =    x5;    base[_VP_VCASTOP2_OFFSET]    =    x6;    base[_VP_VCAVINT_OFFSET]     =    x7;    base[_VP_VCATHRLD_OFFSET]    =    x8;    base[_VP_VCAEVTCT_OFFSET]    =    x9;    base[_VP_VCBSTRT1_OFFSET]    =    x10;    base[_VP_VCBSTOP1_OFFSET]    =    x11;    base[_VP_VCBSTRT2_OFFSET]    =    x12;    base[_VP_VCBSTOP2_OFFSET]    =    x13;    base[_VP_VCBVINT_OFFSET]     =    x14;    base[_VP_VCBTHRLD_OFFSET]    =    x15;    base[_VP_VCBEVTCT_OFFSET]    =    x16;    base[_VP_TSICTL_OFFSET]       =    x17;    base[_VP_TSICLKINITL_OFFSET]  =    x18;    base[_VP_TSICLKINITM_OFFSET]  =    x19;    base[_VP_TSISTCMPL_OFFSET]    =    x20;    base[_VP_TSISTCMPM_OFFSET]    =    x21;    base[_VP_TSISTMSKL_OFFSET]    =    x22;    base[_VP_TSISTMSKM_OFFSET]    =    x23;    base[_VP_TSITICKS_OFFSET]     =    x24;    base[_VP_VCACTL_OFFSET]      =    x25;    base[_VP_VCBCTL_OFFSET]      =    x26;    IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*//* Note: VCACTL is also included in VP_configCaptureTSI();                    *//*----------------------------------------------------------------------------*/IDEF void VP_configCaptureChA(VP_Handle hVp, VP_ConfigCaptureChA *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x3,x4,x5,x6,x7,x8,x9,x10;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x3  =  config->vcastrt1;   x4  =  config->vcastop1;   x5  =  config->vcastrt2;   x6  =  config->vcastop2;   x7  =  config->vcavint;   x8  =  config->vcathrld;   x9  =  config->vcaevtct;   x10 =  config->vcactl;   base[_VP_VCASTRT1_OFFSET]    =    x3;  base[_VP_VCASTOP1_OFFSET]    =    x4;    base[_VP_VCASTRT2_OFFSET]    =    x5;    base[_VP_VCASTOP2_OFFSET]    =    x6;    base[_VP_VCAVINT_OFFSET]     =    x7;    base[_VP_VCATHRLD_OFFSET]    =    x8;    base[_VP_VCAEVTCT_OFFSET]    =    x9;    base[_VP_VCACTL_OFFSET]      =    x10;    IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*//* Note: VCACTL is also included in VP_configCaptureChannelA();               *//*----------------------------------------------------------------------------*/IDEF void VP_configCaptureTSI(VP_Handle hVp, VP_ConfigCaptureTSI *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x15,x16,x17,x18,x19,x20,x21,x22,x23;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x15 =  config->tsictl;   x16 =  config->tsiclkinitl;   x17 =  config->tsiclkinitm;  x18 =  config->tsistcmpl;   x19 =  config->tsistcmpm;  x20 =  config->tsistmskl;   x21 =  config->tsistmskm;  x22 =  config->tsiticks;   x23 =  config->vcactl;   base[_VP_TSICTL_OFFSET]       =    x15;    base[_VP_TSICLKINITL_OFFSET]  =    x16;    base[_VP_TSICLKINITM_OFFSET]  =    x17;    base[_VP_TSISTCMPL_OFFSET]    =    x18;    base[_VP_TSISTCMPM_OFFSET]    =    x19;    base[_VP_TSISTMSKL_OFFSET]    =    x20;    base[_VP_TSISTMSKM_OFFSET]    =    x21;    base[_VP_TSITICKS_OFFSET]     =    x22;    base[_VP_VCACTL_OFFSET]      =    x23;    IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*/IDEF void VP_configCaptureChB(VP_Handle hVp, VP_ConfigCaptureChB *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x9,x10,x11,x12,x13,x14,x15,x16;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x9  =  config->vcbstrt1;   x10 =  config->vcbstop1;   x11 =  config->vcbstrt2;   x12 =  config->vcbstop2;   x13 =  config->vcbvint;   x14 =  config->vcbthrld;   x15 =  config->vcbevtct;   x16 =  config->vcbctl;   base[_VP_VCBSTRT1_OFFSET]    =    x9;    base[_VP_VCBSTOP1_OFFSET]    =    x10;    base[_VP_VCBSTRT2_OFFSET]    =    x11;    base[_VP_VCBSTOP2_OFFSET]    =    x12;    base[_VP_VCBVINT_OFFSET]     =    x13;    base[_VP_VCBTHRLD_OFFSET]    =    x14;    base[_VP_VCBEVTCT_OFFSET]    =    x15;    base[_VP_VCBCTL_OFFSET]      =    x16;    IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*/IDEF void VP_configDisplay(VP_Handle hVp, VP_ConfigDisplay *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x25,x26,x27,x28,x29,x30,x31,x32,x33,x34,x35,x36,x37,x38;  register int x39,x40,x41,x42,x43,x44,x45,x46,x47,x48,x49,x50,x51;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x25 =  config->vdfrmsz;   x26 =  config->vdhblnk;  x27 =  config->vdvblks1;    x28 =  config->vdvblke1;  x29 =  config->vdvblks2;   x30 =  config->vdvblke2;  x31 =  config->vdimoff1;   x32 =  config->vdimgsz1;   x33 =  config->vdimoff2;   x34 =  config->vdimgsz2;   x35 =  config->vdfldt1;   x36 =  config->vdfldt2;   x37 =  config->vdthrld;   x38 =  config->vdhsync;  x39 =  config->vdvsyns1;   x40 =  config->vdvsyne1;   x41 =  config->vdvsyns2;   x42 =  config->vdvsyne2;   x43 =  config->vdreload;   x44 =  config->vddispevt;  x45 =  config->vdclip;  x46 =  config->vddefval;  x47 =  config->vdvint;  x48 =  config->vdfbit;   x49 =  config->vdvbit1;   x50 =  config->vdvbit2;   x51 =  config->vdctl;   base[_VP_VDFRMSZ_OFFSET]   =    x25;  base[_VP_VDHBLNK_OFFSET]   =    x26;    base[_VP_VDVBLKS1_OFFSET]  =    x27;    base[_VP_VDVBLKE1_OFFSET]  =    x28;    base[_VP_VDVBLKS2_OFFSET]  =    x29;    base[_VP_VDVBLKE2_OFFSET]  =    x30;    base[_VP_VDIMGOFF1_OFFSET] =   x31;    base[_VP_VDIMGSZ1_OFFSET]  =    x32;    base[_VP_VDIMGOFF2_OFFSET] =   x33;    base[_VP_VDIMGSZ2_OFFSET]  =    x34;    base[_VP_VDFLDT1_OFFSET]   =    x35;    base[_VP_VDFLDT2_OFFSET]   =    x36;    base[_VP_VDTHRLD_OFFSET]   =    x37;    base[_VP_VDHSYNC_OFFSET]   =    x38;    base[_VP_VDVSYNS1_OFFSET]  =    x39;    base[_VP_VDVSYNE1_OFFSET]  =    x40;    base[_VP_VDVSYNS2_OFFSET]  =    x41;    base[_VP_VDVSYNE2_OFFSET]  =    x42;    base[_VP_VDRELOAD_OFFSET]  =    x43;    base[_VP_VDDISPEVT_OFFSET] =    x44;    base[_VP_VDCLIP_OFFSET]    =    x45;    base[_VP_VDDEFVAL_OFFSET]  =    x46;    base[_VP_VDVINT_OFFSET]    =    x47;    base[_VP_VDFBIT_OFFSET]    =    x48;    base[_VP_VDVBIT1_OFFSET]   =    x49;    base[_VP_VDVBIT2_OFFSET]   =    x50;    base[_VP_VDCTL_OFFSET]     =    x51;    IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*/IDEF void VP_configGpio(VP_Handle hVp, VP_ConfigGpio *config) {  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);  register int x49,x50,x51,x52,x53,x54,x55,x56;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */  x49 =  config->pfunc;   x50 =  config->pdir;  x51 =  config->pdout;  x52 =  config->pdset;  x53 =  config->pdclr;  x54 =  config->pien;  x55 =  config->pipol;  x56 =  config->piclr;  base[_VP_PFUNC_OFFSET]  =    x49;  base[_VP_PDIR_OFFSET]   =    x50;  base[_VP_PDOUT_OFFSET]  =    x51;  base[_VP_PDSET_OFFSET]  =    x52;  base[_VP_PDCLR_OFFSET]  =    x53;  base[_VP_PIEN_OFFSET]   =    x54;  base[_VP_PIPOL_OFFSET]  =    x55;  base[_VP_PICLR_OFFSET]  =    x56;  IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*/IDEF void VP_getConfig(VP_Handle hVp, VP_Config *config){  Uint32 gie;  volatile Uint32 *base = (volatile Uint32 *)(hVp->baseAddr);//  volatile VP_Config* cfg = (volatile VP_Config*)config;  register int x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19;  register int x20,x21,x22,x23,x24,x25,x26,x27,x28,x29,x30,x31,x32,x33,x34,x35,x36;  register int x37,x38,x39,x40,x41,x42,x43,x44,x45,x46,x47,x48,x49,x50,x51,x52,x53;  register int x54,x55,x56,x57,x58,x59,x60,x61;  gie = IRQ_globalDisable();  /* the compiler generates more efficient code if the loads */  /* and stores are grouped together rather than intermixed  */	  x0   =   base[_VP_VPCTL_OFFSET];  x1   =   base[_VP_VPIE_OFFSET];    x2   =   base[_VP_VPIS_OFFSET];    x3   =   base[_VP_VCACTL_OFFSET];    x4   =   base[_VP_VCASTRT1_OFFSET];    x5   =   base[_VP_VCASTOP1_OFFSET];    x6   =   base[_VP_VCASTRT2_OFFSET];    x7   =   base[_VP_VCASTOP2_OFFSET];    x8   =   base[_VP_VCAVINT_OFFSET];    x9   =   base[_VP_VCATHRLD_OFFSET];    x10  =   base[_VP_VCAEVTCT_OFFSET];    x11  =   base[_VP_VCBCTL_OFFSET];    x12  =   base[_VP_VCBSTRT1_OFFSET];    x13  =   base[_VP_VCBSTOP1_OFFSET];    x14  =   base[_VP_VCBSTRT2_OFFSET];    x15  =   base[_VP_VCBSTOP2_OFFSET];    x16  =   base[_VP_VCBVINT_OFFSET];    x17  =   base[_VP_VCBTHRLD_OFFSET];    x18  =   base[_VP_VCBEVTCT_OFFSET];    x19  =   base[_VP_TSICTL_OFFSET];    x20  =   base[_VP_TSICLKINITL_OFFSET];    x21  =   base[_VP_TSICLKINITM_OFFSET];    x22  =   base[_VP_TSISTCMPL_OFFSET];    x23  =   base[_VP_TSISTCMPM_OFFSET];    x24  =   base[_VP_TSISTMSKL_OFFSET];    x25  =   base[_VP_TSISTMSKM_OFFSET];    x26  =   base[_VP_TSITICKS_OFFSET];    x27  =   base[_VP_VDCTL_OFFSET];    x28  =   base[_VP_VDFRMSZ_OFFSET];    x29  =   base[_VP_VDHBLNK_OFFSET];    x30  =   base[_VP_VDVBLKS1_OFFSET];    x31  =   base[_VP_VDVBLKE1_OFFSET];    x32  =   base[_VP_VDVBLKS2_OFFSET];    x33  =   base[_VP_VDVBLKE2_OFFSET];    x34  =   base[_VP_VDIMGOFF1_OFFSET];    x35  =   base[_VP_VDIMGSZ1_OFFSET];    x36  =   base[_VP_VDIMGOFF2_OFFSET];    x37  =   base[_VP_VDIMGSZ2_OFFSET];    x38  =   base[_VP_VDFLDT1_OFFSET];    x39  =   base[_VP_VDFLDT2_OFFSET];    x40  =   base[_VP_VDTHRLD_OFFSET];    x41  =   base[_VP_VDHSYNC_OFFSET];    x42  =   base[_VP_VDVSYNS1_OFFSET];    x43  =   base[_VP_VDVSYNE1_OFFSET];    x44  =   base[_VP_VDVSYNS2_OFFSET];    x45  =   base[_VP_VDVSYNE2_OFFSET];    x46  =   base[_VP_VDRELOAD_OFFSET];    x47  =   base[_VP_VDDISPEVT_OFFSET];    x48  =   base[_VP_VDCLIP_OFFSET];    x49  =   base[_VP_VDDEFVAL_OFFSET];    x50  =   base[_VP_VDVINT_OFFSET];    x51  =   base[_VP_VDFBIT_OFFSET];    x52  =   base[_VP_VDVBIT1_OFFSET];    x53  =   base[_VP_VDVBIT2_OFFSET];    x54  =   base[_VP_PFUNC_OFFSET];    x55  =   base[_VP_PDIR_OFFSET];    x56  =   base[_VP_PDOUT_OFFSET];    x57  =   base[_VP_PDSET_OFFSET];    x58  =   base[_VP_PDCLR_OFFSET];    x59  =   base[_VP_PIEN_OFFSET];    x60  =   base[_VP_PIPOL_OFFSET];    x61  =   base[_VP_PICLR_OFFSET];      config->port->vpctl         =  x0;  config->port->vpie          =  x1;    config->port->vpis          =  x2;    config->capture->vcactl     =  x3;    config->capture->vcastrt1   =  x4;    config->capture->vcastop1   =  x5;    config->capture->vcastrt2   =  x6;    config->capture->vcastop2   =  x7;    config->capture->vcavint    =  x8;    config->capture->vcathrld   =  x9;    config->capture->vcaevtct   =  x10;    config->capture->vcbctl     =  x11;    config->capture->vcbstrt1   =  x12;    config->capture->vcbstop1   =  x13;    config->capture->vcbstrt2   =  x14;    config->capture->vcbstop2   =  x15;    config->capture->vcbvint    =  x16;    config->capture->vcbthrld   =  x17;    config->capture->vcbevtct   =  x18;    config->capture->tsictl      =  x19;    config->capture->tsiclkinitl =  x20;    config->capture->tsiclkinitm =  x21;    config->capture->tsistcmpl   =  x22;    config->capture->tsistcmpm   =  x23;    config->capture->tsistmskl   =  x24;    config->capture->tsistmskm   =  x25;    config->capture->tsiticks    =  x26;    config->display->vdctl      =  x27;    config->display->vdfrmsz    =  x28;    config->display->vdhblnk    =  x29;    config->display->vdvblks1   =  x30;    config->display->vdvblke1   =  x31;    config->display->vdvblks2   =  x32;    config->display->vdvblke2   =  x33;    config->display->vdimoff1   =  x34;    config->display->vdimgsz1   =  x35;    config->display->vdimoff2   =  x36;    config->display->vdimgsz2   =  x37;    config->display->vdfldt1    =  x38;    config->display->vdfldt2    =  x39;    config->display->vdthrld    =  x40;    config->display->vdhsync    =  x41;    config->display->vdvsyns1   =  x42;    config->display->vdvsyne1   =  x43;    config->display->vdvsyns2   =  x44;    config->display->vdvsyne2   =  x45;    config->display->vdreload   =  x46;    config->display->vddispevt  =  x47;    config->display->vdclip     =  x48;    config->display->vddefval   =  x49;    config->display->vdvint     =  x50;    config->display->vdfbit     =  x51;    config->display->vdvbit1    =  x52;    config->display->vdvbit2    =  x53;    config->gpio->pfunc         =  x54;    config->gpio->pdir          =  x55;    config->gpio->pdout         =  x56;    config->gpio->pdset         =  x57;    config->gpio->pdclr         =  x58;    config->gpio->pien          =  x59;    config->gpio->pipol         =  x60;    config->gpio->piclr         =  x61;                                     IRQ_globalRestore(gie);}/*----------------------------------------------------------------------------*/#endif /* USEDEFS */#endif /* MCASP_SUPPORT */#endif /* _CSL_MCASP_H_ *//******************************************************************************\* End of csl_mcasp.h\******************************************************************************/