-- simulation model.--LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.numeric_std.ALL;ENTITY testleijia1 ISEND testleijia1;ARCHITECTURE behavior OF testleijia1 IS 	COMPONENT leijia1	port(A, res,clock : in std_logic;        Q1 ,cout1 : out std_logic);	END COMPONENT;        constant clkcle:time:=10 ns;	SIGNAL clk :  std_logic;	SIGNAL res :  std_logic;	SIGNAL A :  std_logic;	SIGNAL Q1 :  std_logic;	SIGNAL cout1 :  std_logic;BEGIN	uut: leijia1 PORT MAP(		 A,		 res,		 clk,		 Q1,		 cout1	);--clk_gen   clk_gen: process     begin        clk<='1';         wait for clkcle/4;	loop         clk<='0';	wait for clkcle/2;	clk<='1';	wait for clkcle/2;       end loop;    end process;   -- *** Test Bench - User Defined Section ***   tb : PROCESS      BEGIN     -- din<=(others=>'0')      res<='0';       A<='0';      wait for 10*clkcle;      res<='1';         wait for clkcle;  A<='1';      wait for 5*clkcle;  A<='0';      wait for 5*clkcle;  A<='1';      wait; -- will wait forever   END PROCESS;-- *** End Test Bench - User Defined Section ***END;