library ieee;
use ieee.std_logic_1164.all;
entity crc is
port(clk,s_in,reset:in std_logic;
       q:out std_logic_vector(15 downto 0));
end crc;
architecture crc_arch of crc is
signal t1,t2,t3:std_logic;
signal d_new:std_logic_vector(15 downto 0);
begin
t1<=d_new(0) xor s_in;
t2<=d_new(11) xor '1';
t3<=d_new(4) xor '1';
process(clk,reset)
begin
if clk'event and clk='1'then
if reset='1'then
d_new<="0000000000000000";
elsif t1='1'then
d_new<=t1&d_new(15 downto 12)&t2&d_new(10 downto 5)&t3&d_new(3 downto 1);
elsif t1='0'then
d_new<=t1&d_new(15 downto 1);
end if;
end if;
end process;
q<=d_new;
end crc_arch;
crc讀數時q從小到大讀數，因為移位存儲器結構所致