/*********************************************************************************************************
** @file:    core_cm0.h
** @purpose: CMSIS Cortex-M0 Core Peripheral Access Layer Header File
** @version: V1.20
** @date:    22. May 2009
**--------------------------------------------------------------------------------------------------------
**
** Copyright (C) 2009 ARM Limited. All rights reserved.
**
** ARM Limited (ARM) is supplying this software for use with Cortex-Mx 
** processor based microcontrollers.  This file can be freely distributed 
** within development tools that are supporting such ARM based processors. 
**
** THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
** OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
** ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
** CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
**
*********************************************************************************************************/

#ifndef __CM0_CORE_H__
#define __CM0_CORE_H__

#ifdef __cplusplus
 extern "C" {
#endif 

#define __CM0_CMSIS_VERSION_MAIN  (0x01)      /*!< [31:16] CMSIS HAL main version                       */
#define __CM0_CMSIS_VERSION_SUB   (0x20)      /*!< [15:0]  CMSIS HAL sub version                        */
#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)
                                              /*!< CMSIS HAL version number                             */

#define __CORTEX_M                (0x00)      /*!< Cortex core                                          */



#include <stdint.h>                           /* Include standard types                                 */

#if defined (__ICCARM__)
    #include <intrinsics.h>                   /* IAR Intrinsics                                         */
#endif


#ifndef __NVIC_PRIO_BITS
    #define __NVIC_PRIO_BITS    2             /*!< standard definition for NVIC Priority Bits           */
#endif


/*
 *  IO definitions
 *
 *  define access restrictions to peripheral registers
 */

#ifdef __cplusplus
#define     __I     volatile                  /*!< defines 'read only' permissions                      */
#else
#define     __I     volatile const            /*!< defines 'read only' permissions                      */
#endif
#define     __O     volatile                  /*!< defines 'write only' permissions                     */
#define     __IO    volatile                  /*!< defines 'read / write' permissions                   */



/*********************************************************************************************************
  Register Abstraction
*********************************************************************************************************/


/*
 *  System Reset
 */
#define NVIC_VECTRESET              0         /*!< Vector Reset Bit                                     */
#define NVIC_SYSRESETREQ            2         /*!< System Reset Request                                 */
#define NVIC_AIRCR_VECTKEY    (0x5FA << 16)   /*!< AIRCR Key for write access                           */
#define NVIC_AIRCR_ENDIANESS        15        /*!< Endianess                                            */


/*
 *  memory mapping struct for Nested Vectored Interrupt Controller (NVIC)
 */
typedef struct
{
    __IO uint32_t ISER[1];                    /*!< Interrupt Set Enable Register                        */
         uint32_t RESERVED0[31];
    __IO uint32_t ICER[1];                    /*!< Interrupt Clear Enable Register                      */
         uint32_t RSERVED1[31];
    __IO uint32_t ISPR[1];                    /*!< Interrupt Set Pending Register                       */
         uint32_t RESERVED2[31];
    __IO uint32_t ICPR[1];                    /*!< Interrupt Clear Pending Register                     */
         uint32_t RESERVED3[31];
         uint32_t RESERVED4[64];
    __IO uint32_t IPR[8];                     /*!< Interrupt Priority Register                          */
}  NVIC_Type;


/*
 *  memory mapping struct for System Control Block
 */
typedef struct
{
    __I  uint32_t CPUID;                      /*!< CPU ID Base Register                                 */
    __IO uint32_t ICSR;                       /*!< Interrupt Control State Register                     */
         uint32_t RESERVED0;
    __IO uint32_t AIRCR;                      /*!< Application Interrupt / Reset Control Register       */
    __IO uint32_t SCR;                        /*!< System Control Register                              */
    __IO uint32_t CCR;                        /*!< Configuration Control Register                       */
         uint32_t RESERVED1;
    __IO uint32_t SHP[2];                     /*!< System Handlers Priority Registers. [0] is RESERVED  */
    __IO uint32_t SHCSR;                      /*!< System Handler Control and State Register            */
         uint32_t RESERVED2[2];
    __IO uint32_t DFSR;                       /*!< Debug Fault Status Register                          */
} SCB_Type;


/*
 *  memory mapping struct for SysTick
 */
typedef struct
{
    __IO uint32_t CTRL;                       /*!< SysTick Control and Status Register                  */
    __IO uint32_t LOAD;                       /*!< SysTick Reload Value Register                        */
    __IO uint32_t VAL;                        /*!< SysTick Current Value Register                       */
    __I  uint32_t CALIB;                      /*!< SysTick Calibration Register                         */
} SysTick_Type;



/*
 *  Core Debug Register
 */
typedef struct
{
    __IO uint32_t DHCSR;                      /*!< Debug Halting Control and Status Register            */
    __O  uint32_t DCRSR;                      /*!< Debug Core Register Selector Register                */
    __IO uint32_t DCRDR;                      /*!< Debug Core Register Data Register                    */
    __IO uint32_t DEMCR;                      /*!< Debug Exception and Monitor Control Register         */
} CoreDebug_Type;


/*
 *  Memory mapping of Cortex-M0 Hardware
 */
#define SCS_BASE            (0xE000E000)                         /*!< System Control Space Base Address */
#define CoreDebug_BASE      (0xE000EDF0)                         /*!< Core Debug Base Address           */
#define SysTick_BASE        (SCS_BASE +  0x0010)                 /*!< SysTick Base Address              */
#define NVIC_BASE           (SCS_BASE +  0x0100)                 /*!< NVIC Base Address                 */
#define SCB_BASE            (SCS_BASE +  0x0D00)                 /*!< System Control Block Base Address */

#define SCB                 ((SCB_Type *)        SCB_BASE)       /*!< SCB configuration struct          */
#define SysTick             ((SysTick_Type *)    SysTick_BASE)   /*!< SysTick configuration struct      */
#define NVIC                ((NVIC_Type *)       NVIC_BASE)      /*!< NVIC configuration struct         */
#define CoreDebug           ((CoreDebug_Type *)  CoreDebug_BASE) /*!< Core Debug configuration struct   */


/*********************************************************************************************************
  Hardware Abstraction Layer
*********************************************************************************************************/


#if defined ( __CC_ARM   )
    #define __ASM            __asm            /*!< asm keyword for ARM Compiler                         */
    #define __INLINE         __inline         /*!< inline keyword for ARM Compiler                      */

#elif defined ( __ICCARM__ )
    #define __ASM           __asm             /*!< asm keyword for IAR Compiler                         */
    #define __INLINE        inline            /*!< inline keyword for IAR Compiler. Only avaiable in    */
                                              /* High optimization mode!                                */

#elif defined   (  __GNUC__  )
    #define __ASM            __asm            /*!< asm keyword for GNU Compiler                         */
    #define __INLINE         inline           /*!< inline keyword for GNU Compiler                      */

#elif defined   (  __TASKING__  )
    #define __ASM            __asm            /*!< asm keyword for TASKING Compiler                     */
    #define __INLINE         inline           /*!< inline keyword for TASKING Compiler                  */

#endif


/*********************************************************************************************************
  Compiler specific Intrinsics
*********************************************************************************************************/

/*
 *  RealView Compiler
 */
#if defined ( __CC_ARM   )

/*
 *  ARM armcc specific functions
 */
#define __enable_fault_irq                __enable_fiq
#define __disable_fault_irq               __disable_fiq

#define __NOP                             __nop
#define __WFI                             __wfi
#define __WFE                             __wfe
#define __SEV                             __sev
#define __ISB()                           __isb(0)
#define __DSB()                           __dsb(0)
#define __DMB()                           __dmb(0)
#define __REV                             __rev

/* intrinsic void __enable_irq();                                 */
/* intrinsic void __disable_irq();                                */

/*********************************************************************************************************
** @brief  Return the Process Stack Pointer
**
** @param  none
** @return uint32_t ProcessStackPointer
**
** Return the actual process stack pointer
*********************************************************************************************************/
extern uint32_t __get_PSP(void);

/*********************************************************************************************************
** @brief  Set the Process Stack Pointer
**
** @param  uint32_t Process Stack Pointer
** @return none
**
** Assign the value ProcessStackPointer to the MSP 
** (process stack pointer) Cortex processor register
*********************************************************************************************************/
extern void __set_PSP(uint32_t topOfProcStack);

/*********************************************************************************************************
** @brief  Return the Main Stack Pointer
**
** @param  none
** @return uint32_t Main Stack Pointer
**
** Return the current value of the MSP (main stack pointer)
** Cortex processor register
*********************************************************************************************************/
extern uint32_t __get_MSP(void);

/*********************************************************************************************************
** @brief  Set the Main Stack Pointer
**
** @param  uint32_t Main Stack Pointer
** @return none
**
** Assign the value mainStackPointer to the MSP 
** (main stack pointer) Cortex processor register
*********************************************************************************************************/
extern void __set_MSP(uint32_t topOfMainStack);

/*********************************************************************************************************
** @brief  Reverse byte order in unsigned short value
**
** @param  uint16_t value to reverse
** @return uint32_t reversed value
**
** Reverse byte order in unsigned short value
*********************************************************************************************************/
extern uint32_t __REV16(uint16_t value);

/*********************************************************************************************************
** @brief  Reverse byte order in signed short value with sign extension to integer
**
** @param  int16_t value to reverse
** @return int32_t reversed value
**
** Reverse byte order in signed short value with sign extension to integer
*********************************************************************************************************/
extern int32_t __REVSH(int16_t value);


#if (__ARMCC_VERSION < 400000)