`timescale 1ns/10ps     

`define width 15
module csa52(//input
             a1,a2,a3,a4,a5,
             
            //output 
             sum);
input  [`width-3:0] a1,a2,a3,a4,a5;
output [`width:0] sum;


wire [`width:0] cr_tmp;
wire [`width:0] sr_tmp;     
wire [`width:0] cl_tmp;
wire [`width:0] sl_tmp;             

wire [`width:0] a1m=(a1[`width-3]==1)? { {3{1'b1}},a1}:{3'b0,a1};
wire [`width:0] a2m=(a2[`width-3]==1)? { {3{1'b1}},a2}:{3'b0,a2};
wire [`width:0] a3m=(a3[`width-3]==1)? { {3{1'b1}},a3}:{3'b0,a3};
wire [`width:0] a4m=(a4[`width-3]==1)? { {3{1'b1}},a4}:{3'b0,a4};
wire [`width:0] a5m=(a5[`width-3]==1)? { {3{1'b1}},a5}:{3'b0,a5};
 
assign sr_tmp=a1m ^ a2m ^ a3m;
assign cr_tmp=(a1m & a2m) | (a1m & a3m) | (a2m & a3m);

wire [`width+1:0] cr={cr_tmp,1'b0};
wire [`width+1:0] sr={1'b0,sr_tmp};
//for test purpose mark it after ok!
//wire [`width:0] test0={cr_tmp,1'b0}+{1'b0,sr_tmp};

 
assign sl_tmp= a4m ^ a5m ;
assign cl_tmp= a4m & a5m ;
 
 
wire [`width:0] cl={cl_tmp,1'b0};
wire [`width:0] sl={1'b0,sl_tmp};
//wire [`width:0] test1=cl+sl;

wire [`width:0] c_tmp1;
wire [`width:0] s_tmp1;
 
assign  s_tmp1= sr ^ cr ^ sl;
assign  c_tmp1= (sr & cr) | (sr & sl) | (cr & sl);
 

wire [`width:0] c_tmp3={c_tmp1,1'b0};
wire [`width:0] s_tmp3={1'b0,s_tmp1};
wire  [`width:0] c_tmp4;
wire  [`width:0] s_tmp4;
  
assign s_tmp4=cl ^ c_tmp3 ^ s_tmp3;
assign c_tmp4=(cl & c_tmp3) | (cl & s_tmp3) | (c_tmp3 & s_tmp3);
 
wire [`width:0] c_tmp5={c_tmp4,1'b0};
wire [`width:0] s_tmp5={1'b0,s_tmp4};
wire [`width:0] sum=c_tmp5+s_tmp5;
 

endmodule