`timescale 1ns/10ps

module packer(
       //input                     
       clk,nrst,
       dcten,idle,                   
       den,dc,eob,zero15,
       lumenb,chromenb,
       din,din_sign,
       //dc diff part  
       ldccode,ldclength, 
       cdccode,cdclength,  
       //ac part                    
       lcode,ccode,
       llength,clength,                  
       //output
       jpg_en,
       jpg_wptr,                    
       jpg_out);                  
                                
input  clk,nrst;                   
input  dcten,idle;
input  den,dc,eob,zero15,lumenb,chromenb;                        
input  [7:0]  din; 
input         din_sign;                 
//dc diff part  
input  [8:0]  ldccode;
input  [3:0]  ldclength;
input  [8:0]  cdccode;
input  [3:0]  cdclength;
//ac part 
input  [15:0] lcode,ccode;               
input  [3:0]  llength,clength; 

output        jpg_en;
output [3:0]  jpg_wptr;                                   
output [15:0] jpg_out;  
              
reg [23:0] combine_codeword;                                   
reg [7:0]  append;
reg [3:0]  length;
reg [15:0] code;
//=======================================================================
//partI: do combine 
//======================================================================= 
always @(dc or dcten or lumenb or chromenb or ldccode or
         lcode or cdccode or ccode)
begin
   if (lumenb & dcten) 
      if (dc) code={ldccode,7'b0};
      else    code= lcode;
   else if (chromenb & dcten)    
      if (dc) code={cdccode,7'b0};          
      else    code=ccode;
end         

always @(dc or dcten or lumenb or chromenb or ldclength or
         llength or cdclength or clength)
begin
   if (lumenb & dcten) 
      if (dc) length= ldclength;
      else    length= llength;
   else if (chromenb & dcten)    
      if (dc) length= cdclength;          
      else    length= clength;
end         
// Length=0