?? at91rm9200_emac.h
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/* linux/include/asm-arm/arch-at91rm9200/at91rm9200_emac.h
*
* Hardware definition for the emac peripheral in the ATMEL at91rm9200 processor
*
* Generated 01/09/2006 (16:49:36) AT91 SW Application Group from EMAC_1794A V1.4
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __AT91RM9200_EMAC_H
#define __AT91RM9200_EMAC_H
/* -------------------------------------------------------- */
/* EMAC ID definitions for AT91RM9200 */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_EMAC
#define AT91C_ID_EMAC 24 /**< Ethernet MAC id */
#endif /* AT91C_ID_EMAC */
/* -------------------------------------------------------- */
/* EMAC Base Address definitions for AT91RM9200 */
/* -------------------------------------------------------- */
#define AT91C_BASE_EMAC 0xFFFBC000 /**< EMAC base address */
/* -------------------------------------------------------- */
/* PIO definition for EMAC hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PA11_ECRS_ECRSDV (1 << 11) /**< Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
#define AT91C_PA15_EMDC (1 << 15) /**< Ethernet MAC Management Data Clock */
#define AT91C_PA16_EMDIO (1 << 16) /**< Ethernet MAC Management Data Input/Output */
#define AT91C_PA12_ERX0 (1 << 12) /**< Ethernet MAC Receive Data 0 */
#define AT91C_PA13_ERX1 (1 << 13) /**< Ethernet MAC Receive Data 1 */
#define AT91C_PA14_ERXER (1 << 14) /**< Ethernet MAC Receive Error */
#define AT91C_PA9_ETX0 (1 << 9) /**< Ethernet MAC Transmit Data 0 */
#define AT91C_PA10_ETX1 (1 << 10) /**< Ethernet MAC Transmit Data 1 */
#define AT91C_PA7_ETXCK_EREFCK (1 << 7) /**< Ethernet MAC Transmit Clock/Reference Clock */
#define AT91C_PA8_ETXEN (1 << 8) /**< Ethernet MAC Transmit Enable */
/* -------------------------------------------------------- */
/* Register offset definition for EMAC hardware peripheral */
/* -------------------------------------------------------- */
#define EMAC_CTL (0x0000) /**< Network Control Register */
#define EMAC_CFG (0x0004) /**< Network Configuration Register */
#define EMAC_SR (0x0008) /**< Network Status Register */
#define EMAC_TAR (0x000C) /**< Transmit Address Register */
#define EMAC_TCR (0x0010) /**< Transmit Control Register */
#define EMAC_TSR (0x0014) /**< Transmit Status Register */
#define EMAC_RBQP (0x0018) /**< Receive Buffer Queue Pointer */
#define EMAC_RSR (0x0020) /**< Receive Status Register */
#define EMAC_ISR (0x0024) /**< Interrupt Status Register */
#define EMAC_IER (0x0028) /**< Interrupt Enable Register */
#define EMAC_IDR (0x002C) /**< Interrupt Disable Register */
#define EMAC_IMR (0x0030) /**< Interrupt Mask Register */
#define EMAC_MAN (0x0034) /**< PHY Maintenance Register */
#define EMAC_FRA (0x0040) /**< Frames Transmitted OK Register */
#define EMAC_SCOL (0x0044) /**< Single Collision Frame Register */
#define EMAC_MCOL (0x0048) /**< Multiple Collision Frame Register */
#define EMAC_OK (0x004C) /**< Frames Received OK Register */
#define EMAC_SEQE (0x0050) /**< Frame Check Sequence Error Register */
#define EMAC_ALE (0x0054) /**< Alignment Error Register */
#define EMAC_DTE (0x0058) /**< Deferred Transmission Frame Register */
#define EMAC_LCOL (0x005C) /**< Late Collision Register */
#define EMAC_ECOL (0x0060) /**< Excessive Collision Register */
#define EMAC_CSE (0x0064) /**< Carrier Sense Error Register */
#define EMAC_TUE (0x0068) /**< Transmit Underrun Error Register */
#define EMAC_CDE (0x006C) /**< Code Error Register */
#define EMAC_ELR (0x0070) /**< Excessive Length Error Register */
#define EMAC_RJB (0x0074) /**< Receive Jabber Register */
#define EMAC_USF (0x0078) /**< Undersize Frame Register */
#define EMAC_SQEE (0x007C) /**< SQE Test Error Register */
#define EMAC_DRFC (0x0080) /**< Discarded RX Frame Register */
#define EMAC_HSH (0x0090) /**< Hash Address High[63:32] */
#define EMAC_HSL (0x0094) /**< Hash Address Low[31:0] */
#define EMAC_SA1L (0x0098) /**< Specific Address 1 Low, First 4 bytes */
#define EMAC_SA1H (0x009C) /**< Specific Address 1 High, Last 2 bytes */
#define EMAC_SA2L (0x00A0) /**< Specific Address 2 Low, First 4 bytes */
#define EMAC_SA2H (0x00A4) /**< Specific Address 2 High, Last 2 bytes */
#define EMAC_SA3L (0x00A8) /**< Specific Address 3 Low, First 4 bytes */
#define EMAC_SA3H (0x00AC) /**< Specific Address 3 High, Last 2 bytes */
#define EMAC_SA4L (0x00B0) /**< Specific Address 4 Low, First 4 bytes */
#define EMAC_SA4H (0x00B4) /**< Specific Address 4 High, Last 2 bytesr */
/* -------------------------------------------------------- */
/* Bitfields definition for EMAC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register EMAC_CTL */
#define AT91C_EMAC_LB (0x1 << 0 ) /**< (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
#define AT91C_EMAC_LBL (0x1 << 1 ) /**< (EMAC) Loopback local. */
#define AT91C_EMAC_RE (0x1 << 2 ) /**< (EMAC) Receive enable. */
#define AT91C_EMAC_TE (0x1 << 3 ) /**< (EMAC) Transmit enable. */
#define AT91C_EMAC_MPE (0x1 << 4 ) /**< (EMAC) Management port enable. */
#define AT91C_EMAC_CSR (0x1 << 5 ) /**< (EMAC) Clear statistics registers. */
#define AT91C_EMAC_ISR (0x1 << 6 ) /**< (EMAC) Increment statistics registers. */
#define AT91C_EMAC_WES (0x1 << 7 ) /**< (EMAC) Write enable for statistics registers. */
#define AT91C_EMAC_BP (0x1 << 8 ) /**< (EMAC) Back pressure. */
/* --- Register EMAC_CFG */
#define AT91C_EMAC_SPD (0x1 << 0 ) /**< (EMAC) Speed. */
#define AT91C_EMAC_FD (0x1 << 1 ) /**< (EMAC) Full duplex. */
#define AT91C_EMAC_BR (0x1 << 2 ) /**< (EMAC) Bit rate. */
#define AT91C_EMAC_CAF (0x1 << 4 ) /**< (EMAC) Copy all frames. */
#define AT91C_EMAC_NBC (0x1 << 5 ) /**< (EMAC) No broadcast. */
#define AT91C_EMAC_MTI (0x1 << 6 ) /**< (EMAC) Multicast hash enable */
#define AT91C_EMAC_UNI (0x1 << 7 ) /**< (EMAC) Unicast hash enable. */
#define AT91C_EMAC_BIG (0x1 << 8 ) /**< (EMAC) Receive 1522 bytes. */
#define AT91C_EMAC_EAE (0x1 << 9 ) /**< (EMAC) External address match enable. */
#define AT91C_EMAC_CLK (0x3 << 10) /**< (EMAC) */
#define AT91C_EMAC_CLK_HCLK_8 (0x0 << 10) /**< (EMAC) HCLK divided by 8 */
#define AT91C_EMAC_CLK_HCLK_16 (0x1 << 10) /**< (EMAC) HCLK divided by 16 */
#define AT91C_EMAC_CLK_HCLK_32 (0x2 << 10) /**< (EMAC) HCLK divided by 32 */
#define AT91C_EMAC_CLK_HCLK_64 (0x3 << 10) /**< (EMAC) HCLK divided by 64 */
#define AT91C_EMAC_RTY (0x1 << 12) /**< (EMAC) */
#define AT91C_EMAC_RMII (0x1 << 13) /**< (EMAC) */
/* --- Register EMAC_SR */
#define AT91C_EMAC_MDIO (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_IDLE (0x1 << 2 ) /**< (EMAC) */
/* --- Register EMAC_TCR */
#define AT91C_EMAC_LEN (0x7FF << 0 ) /**< (EMAC) */
#define AT91C_EMAC_NCRC (0x1 << 15) /**< (EMAC) */
/* --- Register EMAC_TSR */
#define AT91C_EMAC_OVR (0x1 << 0 ) /**< (EMAC) */
#define AT91C_EMAC_COL (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_RLE (0x1 << 2 ) /**< (EMAC) */
#define AT91C_EMAC_TXIDLE (0x1 << 3 ) /**< (EMAC) */
#define AT91C_EMAC_BNQ (0x1 << 4 ) /**< (EMAC) */
#define AT91C_EMAC_COMP (0x1 << 5 ) /**< (EMAC) */
#define AT91C_EMAC_UND (0x1 << 6 ) /**< (EMAC) */
/* --- Register EMAC_RSR */
#define AT91C_EMAC_BNA (0x1 << 0 ) /**< (EMAC) */
#define AT91C_EMAC_REC (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_OVR (0x1 << 2 ) /**< (EMAC) */
/* --- Register EMAC_ISR */
#define AT91C_EMAC_DONE (0x1 << 0 ) /**< (EMAC) */
#define AT91C_EMAC_RCOM (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_RBNA (0x1 << 2 ) /**< (EMAC) */
#define AT91C_EMAC_TOVR (0x1 << 3 ) /**< (EMAC) */
#define AT91C_EMAC_TUND (0x1 << 4 ) /**< (EMAC) */
#define AT91C_EMAC_RTRY (0x1 << 5 ) /**< (EMAC) */
#define AT91C_EMAC_TBRE (0x1 << 6 ) /**< (EMAC) */
#define AT91C_EMAC_TCOM (0x1 << 7 ) /**< (EMAC) */
#define AT91C_EMAC_TIDLE (0x1 << 8 ) /**< (EMAC) */
#define AT91C_EMAC_LINK (0x1 << 9 ) /**< (EMAC) */
#define AT91C_EMAC_ROVR (0x1 << 10) /**< (EMAC) */
#define AT91C_EMAC_HRESP (0x1 << 11) /**< (EMAC) */
/* --- Register EMAC_IER */
#define AT91C_EMAC_DONE (0x1 << 0 ) /**< (EMAC) */
#define AT91C_EMAC_RCOM (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_RBNA (0x1 << 2 ) /**< (EMAC) */
#define AT91C_EMAC_TOVR (0x1 << 3 ) /**< (EMAC) */
#define AT91C_EMAC_TUND (0x1 << 4 ) /**< (EMAC) */
#define AT91C_EMAC_RTRY (0x1 << 5 ) /**< (EMAC) */
#define AT91C_EMAC_TBRE (0x1 << 6 ) /**< (EMAC) */
#define AT91C_EMAC_TCOM (0x1 << 7 ) /**< (EMAC) */
#define AT91C_EMAC_TIDLE (0x1 << 8 ) /**< (EMAC) */
#define AT91C_EMAC_LINK (0x1 << 9 ) /**< (EMAC) */
#define AT91C_EMAC_ROVR (0x1 << 10) /**< (EMAC) */
#define AT91C_EMAC_HRESP (0x1 << 11) /**< (EMAC) */
/* --- Register EMAC_IDR */
#define AT91C_EMAC_DONE (0x1 << 0 ) /**< (EMAC) */
#define AT91C_EMAC_RCOM (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_RBNA (0x1 << 2 ) /**< (EMAC) */
#define AT91C_EMAC_TOVR (0x1 << 3 ) /**< (EMAC) */
#define AT91C_EMAC_TUND (0x1 << 4 ) /**< (EMAC) */
#define AT91C_EMAC_RTRY (0x1 << 5 ) /**< (EMAC) */
#define AT91C_EMAC_TBRE (0x1 << 6 ) /**< (EMAC) */
#define AT91C_EMAC_TCOM (0x1 << 7 ) /**< (EMAC) */
#define AT91C_EMAC_TIDLE (0x1 << 8 ) /**< (EMAC) */
#define AT91C_EMAC_LINK (0x1 << 9 ) /**< (EMAC) */
#define AT91C_EMAC_ROVR (0x1 << 10) /**< (EMAC) */
#define AT91C_EMAC_HRESP (0x1 << 11) /**< (EMAC) */
/* --- Register EMAC_IMR */
#define AT91C_EMAC_DONE (0x1 << 0 ) /**< (EMAC) */
#define AT91C_EMAC_RCOM (0x1 << 1 ) /**< (EMAC) */
#define AT91C_EMAC_RBNA (0x1 << 2 ) /**< (EMAC) */
#define AT91C_EMAC_TOVR (0x1 << 3 ) /**< (EMAC) */
#define AT91C_EMAC_TUND (0x1 << 4 ) /**< (EMAC) */
#define AT91C_EMAC_RTRY (0x1 << 5 ) /**< (EMAC) */
#define AT91C_EMAC_TBRE (0x1 << 6 ) /**< (EMAC) */
#define AT91C_EMAC_TCOM (0x1 << 7 ) /**< (EMAC) */
#define AT91C_EMAC_TIDLE (0x1 << 8 ) /**< (EMAC) */
#define AT91C_EMAC_LINK (0x1 << 9 ) /**< (EMAC) */
#define AT91C_EMAC_ROVR (0x1 << 10) /**< (EMAC) */
#define AT91C_EMAC_HRESP (0x1 << 11) /**< (EMAC) */
/* --- Register EMAC_MAN */
#define AT91C_EMAC_DATA (0xFFFF << 0 ) /**< (EMAC) */
#define AT91C_EMAC_CODE (0x3 << 16) /**< (EMAC) */
#define AT91C_EMAC_REGA (0x1F << 18) /**< (EMAC) */
#define AT91C_EMAC_PHYA (0x1F << 23) /**< (EMAC) */
#define AT91C_EMAC_RW (0x3 << 28) /**< (EMAC) */
#define AT91C_EMAC_HIGH (0x1 << 30) /**< (EMAC) */
#define AT91C_EMAC_LOW (0x1 << 31) /**< (EMAC) */
#endif /* __AT91RM9200_EMAC_H */
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