/* linux/include/asm-arm/arch-at91rm9200/at91rm9200_st.h
 * 
 * Hardware definition for the st peripheral in the ATMEL at91rm9200 processor
 * 
 * Generated  01/09/2006 (16:49:36) AT91 SW Application Group from ST_1763B V1.1
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91RM9200_ST_H
#define __AT91RM9200_ST_H

/* -------------------------------------------------------- */
/* ST ID definitions for  AT91RM9200           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_SYS
#define AT91C_ID_SYS   	 1 /**< System Peripheral id */
#endif /* AT91C_ID_SYS */

/* -------------------------------------------------------- */
/* ST Base Address definitions for  AT91RM9200   */
/* -------------------------------------------------------- */
#define AT91C_BASE_ST        	0xFFFFFD00 /**< ST base address */

/* -------------------------------------------------------- */
/* PIO definition for ST hardware peripheral */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* Register offset definition for ST hardware peripheral */
/* -------------------------------------------------------- */
#define ST_CR 	(0x0000) 	/**< Control Register */
#define ST_PIMR 	(0x0004) 	/**< Period Interval Mode Register */
#define ST_WDMR 	(0x0008) 	/**< Watchdog Mode Register */
#define ST_RTMR 	(0x000C) 	/**< Real-time Mode Register */
#define ST_SR 	(0x0010) 	/**< Status Register */
#define ST_IER 	(0x0014) 	/**< Interrupt Enable Register */
#define ST_IDR 	(0x0018) 	/**< Interrupt Disable Register */
#define ST_IMR 	(0x001C) 	/**< Interrupt Mask Register */
#define ST_RTAR 	(0x0020) 	/**< Real-time Alarm Register */
#define ST_CRTR 	(0x0024) 	/**< Current Real-time Register */

/* -------------------------------------------------------- */
/* Bitfields definition for ST hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register ST_CR */
#define AT91C_ST_WDRST        (0x1 << 0 ) /**< (ST) Watchdog Timer Restart */
/* --- Register ST_PIMR */
#define AT91C_ST_PIV          (0xFFFF << 0 ) /**< (ST) Watchdog Timer Restart */
/* --- Register ST_WDMR */
#define AT91C_ST_WDV          (0xFFFF << 0 ) /**< (ST) Watchdog Timer Restart */
#define AT91C_ST_RSTEN        (0x1 << 16) /**< (ST) Reset Enable */
#define AT91C_ST_EXTEN        (0x1 << 17) /**< (ST) External Signal Assertion Enable */
/* --- Register ST_RTMR */
#define AT91C_ST_RTPRES       (0xFFFF << 0 ) /**< (ST) Real-time Timer Prescaler Value */
/* --- Register ST_SR */
#define AT91C_ST_PITS         (0x1 << 0 ) /**< (ST) Period Interval Timer Interrupt */
#define AT91C_ST_WDOVF        (0x1 << 1 ) /**< (ST) Watchdog Overflow */
#define AT91C_ST_RTTINC       (0x1 << 2 ) /**< (ST) Real-time Timer Increment */
#define AT91C_ST_ALMS         (0x1 << 3 ) /**< (ST) Alarm Status */
/* --- Register ST_IER */
#define AT91C_ST_PITS         (0x1 << 0 ) /**< (ST) Period Interval Timer Interrupt */
#define AT91C_ST_WDOVF        (0x1 << 1 ) /**< (ST) Watchdog Overflow */
#define AT91C_ST_RTTINC       (0x1 << 2 ) /**< (ST) Real-time Timer Increment */
#define AT91C_ST_ALMS         (0x1 << 3 ) /**< (ST) Alarm Status */
/* --- Register ST_IDR */
#define AT91C_ST_PITS         (0x1 << 0 ) /**< (ST) Period Interval Timer Interrupt */
#define AT91C_ST_WDOVF        (0x1 << 1 ) /**< (ST) Watchdog Overflow */
#define AT91C_ST_RTTINC       (0x1 << 2 ) /**< (ST) Real-time Timer Increment */
#define AT91C_ST_ALMS         (0x1 << 3 ) /**< (ST) Alarm Status */
/* --- Register ST_IMR */
#define AT91C_ST_PITS         (0x1 << 0 ) /**< (ST) Period Interval Timer Interrupt */
#define AT91C_ST_WDOVF        (0x1 << 1 ) /**< (ST) Watchdog Overflow */
#define AT91C_ST_RTTINC       (0x1 << 2 ) /**< (ST) Real-time Timer Increment */
#define AT91C_ST_ALMS         (0x1 << 3 ) /**< (ST) Alarm Status */
/* --- Register ST_RTAR */
#define AT91C_ST_ALMV         (0xFFFFF << 0 ) /**< (ST) Alarm Value Value */
/* --- Register ST_CRTR */
#define AT91C_ST_CRTV         (0xFFFFF << 0 ) /**< (ST) Current Real-time Value */

#endif /* __AT91RM9200_ST_H */