?? ramstart.inc
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#/*************************************************************************/
#/* Constant Definitions */
#/* I/O PORT */
#/*************************************************************************/
.equ rBWSCON , 0x01C80000 /* bus width and wait status control */
.equ rBANKCON0 , 0x01C80004 /* Boot ROM Control */
.equ rBANKCON1 , 0x01C80008 /* BANK1 Control */
.equ rBANKCON2 , 0x01C8000c /* BANK2 Control */
.equ rBANKCON3 , 0x01C80010 /* BANK3 Control */
.equ rBANKCON4 , 0x01C80014 /* BANK4 Control */
.equ rBANKCON5 , 0x01C80018 /* BANK5 Control */
.equ rBANKCON6 , 0x01C8001c /* BANK6 Control */
.equ rBANKCON7 , 0x01C80020 /* BANK7 Control */
.equ rREFRESH , 0x01C80024 /* DRAM/SDRAM Refresh Control */
.equ rBANKSIZE , 0x01C80028 /* Flexible Bank Size */
.equ rMRSRB6 , 0x01C8002c /* Mode Register set for SDRAM */
.equ rMRSRB7 , 0x01C80030 /* Mode Register set for SDRAM */
.equ rPCONA , 0x01d20000 /* Port A */
.equ rPDATA , 0x01d20004
.equ rPCONB , 0x01d20008 /* Port B */
.equ rPDATB , 0x01d2000c
.equ rPCONC , 0x01d20010 /* Port C */
.equ rPDATC , 0x01d20014
.equ rPUPC , 0x01d20018
.equ rPCOND , 0x01d2001c /* Port D */
.equ rPDATD , 0x01d20020
.equ rPUPD , 0x01d20024
.equ rPCONE , 0x01d20028 /* Port E */
.equ rPDATE , 0x01d2002c
.equ rPUPE , 0x01d20030
.equ rPCONF , 0x01d20034 /* Port F */
.equ rPDATF , 0x01d20038
.equ rPUPF , 0x01d2003c
.equ rPCONG , 0x01d20040 /* Port G */
.equ rPDATG , 0x01d20044
.equ rPUPG , 0x01d20048
.equ rSPUCR , 0x01d2004c /* Special Pull-Up Registor Control Register */
.equ rEXTINT , 0x01d20050 /* External Interrupt Control Register */
#/*************************************************************************/
#/* Constant Definitions */
#/* Interrupt Control */
#/*************************************************************************/
.equ INTCON , 0x01e00000
.equ INTPND , 0x01e00004
.equ INTMOD , 0x01e00008
.equ INTMSK , 0x01e0000c
.equ I_ISPR , 0x01e00020
.equ I_CMST , 0x01e0001c
.equ I_PMST , 0x01e00014
#/*************************************************************************/
#/* Constant Definitions */
#/* Watchdog timer */
#/*************************************************************************/
.equ WTCON , 0x01d30000
#/*************************************************************************/
#/* Constant Definitions */
#/* Clock Controller */
#/*************************************************************************/
.equ PLLCON , 0x01d80000
.equ CLKCON , 0x01d80004
.equ LOCKTIME , 0x01d8000c
#/*************************************************************************/
#/* Constant Definitions */
#/* Memory Controller */
#/*************************************************************************/
.equ REFRESH , 0x01c80024
#/*************************************************************************/
#/* Constant Definitions */
#/* System configuration */
#/*************************************************************************/
.equ SYSCFG , 0x01c00000
.equ NCACHBE0 , 0x01c00004
.equ NCACHBE1 , 0x01c00008
#/*************************************************************************/
#/* Constant Definitions */
#/* Pre-defined constants */
#/*************************************************************************/
.equ USERMODE , 0x10
.equ FIQMODE , 0x11
.equ IRQMODE , 0x12
.equ SVCMODE , 0x13
.equ ABORTMODE , 0x17
.equ UNDEFMODE , 0x1b
.equ MODEMASK , 0x1f
.equ NOINT , 0xc0
.equ TIMER0_INT , 0x00002000
.equ LOCKOUT , 0xC0 /* Interrupt lockout value */
.equ LOCK_MSK , 0xC0 /* Interrupt lockout mask value */
.equ MODE_MASK , 0x1F /* Processor Mode Mask */
.equ SUP_MODE , 0x13 /* Supervisor Mode (SVC) */
.equ VECTOR_TABLE , 0x0c032000 /* just 16M Bytes SDRAM. */
.equ VIRTUAL_TABLE , 0x0c032000 /* just 16M Bytes SDRAM. */
.equ _ISR_STARTADDRESS , 0x0c7fff00 /*GCS6(nSCS0):16MByte SDRAM */
#//////////////////////////////////////////////////////////////////////
# Stack Area
.EQU UserStack , _ISR_STARTADDRESS - 0x500
.EQU SVCStack , _ISR_STARTADDRESS - 0x400
.EQU UndefStack , _ISR_STARTADDRESS - 0x300
.EQU AbortStack , _ISR_STARTADDRESS - 0x200
.EQU IRQStack , _ISR_STARTADDRESS - 0x100
.EQU FIQStack , _ISR_STARTADDRESS
# ISR Vector
.EQU HandleReset , _ISR_STARTADDRESS
.EQU HandleUndef , _ISR_STARTADDRESS + 0x04
.EQU HandleSWI , _ISR_STARTADDRESS + 0x08
.EQU HandlePabort , _ISR_STARTADDRESS + 0x0c
.EQU HandleDabort , _ISR_STARTADDRESS + 0x10
.EQU HandleReserved , _ISR_STARTADDRESS + 0x14
.EQU HandleIRQ , _ISR_STARTADDRESS + 0x18
.EQU HandleFIQ , _ISR_STARTADDRESS + 0x1c
.EQU HandleADC , _ISR_STARTADDRESS + 0x20
.EQU HandleRTC , _ISR_STARTADDRESS + 0x24
.EQU HandleUTXD1 , _ISR_STARTADDRESS + 0x28
.EQU HandleUTXD0 , _ISR_STARTADDRESS + 0x2c
.EQU HandleSIO , _ISR_STARTADDRESS + 0x30
.EQU HandleIIC , _ISR_STARTADDRESS + 0x34
.EQU HandleURXD1 , _ISR_STARTADDRESS + 0x38
.EQU HandleURXD0 , _ISR_STARTADDRESS + 0x3c
.EQU HandleTIMER5 , _ISR_STARTADDRESS + 0x40
.EQU HandleTIMER4 , _ISR_STARTADDRESS + 0x44
.EQU HandleTIMER3 , _ISR_STARTADDRESS + 0x48
.EQU HandleTIMER2 , _ISR_STARTADDRESS + 0x4c
.EQU HandleTIMER1 , _ISR_STARTADDRESS + 0x50
.EQU HandleTIMER0 , _ISR_STARTADDRESS + 0x54
.EQU HandleUERR01 , _ISR_STARTADDRESS + 0x58
.EQU HandleWDT , _ISR_STARTADDRESS + 0x5c
.EQU HandleBDMA1 , _ISR_STARTADDRESS + 0x60
.EQU HandleBDMA0 , _ISR_STARTADDRESS + 0x64
.EQU HandleZDMA1 , _ISR_STARTADDRESS + 0x68
.EQU HandleZDMA0 , _ISR_STARTADDRESS + 0x6c
.EQU HandleTICK , _ISR_STARTADDRESS + 0x70
.EQU HandleEINT4567 , _ISR_STARTADDRESS + 0x74
.EQU HandleEINT3 , _ISR_STARTADDRESS + 0x78
.EQU HandleEINT2 , _ISR_STARTADDRESS + 0x7c
.EQU HandleEINT1 , _ISR_STARTADDRESS + 0x80
.EQU HandleEINT0 , _ISR_STARTADDRESS + 0x84
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