; generated by ARM C Compiler, ADS1.2 [Build 805]

; commandline [-O0 -browseinfo "0xff
" -S   -g+ -apcs /interwork -fk -J:cw:]
        CODE32

        AREA ||.text||, CODE, READONLY

find_empty_and_copy_process PROC
|L1.0|
        STMFD    sp!,{r4-r6,lr}
        MOV      r6,#0
        NOP      
|L1.12|
        LDR      r0,|L1.424|
        LDR      r0,[r0,#0]  ; last_pid
        ADD      r0,r0,#1
        LDR      r1,|L1.424|
        STR      r0,[r1,#0]  ; last_pid
        CMP      r0,#0
        BGE      |L1.52|
        MOV      r0,#1
        LDR      r1,|L1.424|
        STR      r0,[r1,#0]  ; last_pid
|L1.52|
        MOV      r5,#0
|L1.56|
        CMP      r5,#0x40
        BGE      |L1.128|
        B        |L1.76|
|L1.68|
        ADD      r5,r5,#1
        B        |L1.56|
|L1.76|
        LDR      r0,|L1.428|
        LDR      r0,[r0,r5,LSL #2]
        CMP      r0,#0
        BEQ      |L1.124|
        LDR      r0,|L1.428|
        LDR      r0,[r0,r5,LSL #2]
        LDR      r0,[r0,#0x220]
        LDR      r1,|L1.424|
        LDR      r1,[r1,#0]  ; last_pid
        CMP      r0,r1
        BNE      |L1.124|
        B        |L1.12|
|L1.124|
        B        |L1.68|
|L1.128|
        MOV      r5,#1
|L1.132|
        CMP      r5,#0x40
        BGE      |L1.416|
        B        |L1.152|
|L1.144|
        ADD      r5,r5,#1
        B        |L1.132|
|L1.152|
        LDR      r0,|L1.428|
        LDR      r0,[r0,r5,LSL #2]
        CMP      r0,#0
        BNE      |L1.412|
        MOV      r0,#0x260
        BL       ms_get_pool
        MOV      r4,r0
        CMP      r4,#0
        BNE      |L1.200|
        MVN      r0,#0xa
|L1.192|
        LDMFD    sp!,{r4-r6,lr}
        BX       lr
|L1.200|
        LDR      r0,|L1.428|
        STR      r4,[r0,r5,LSL #2]
        MOV      r0,#0x400
        BL       ms_get_pool
        MOV      r6,r0
        CMP      r6,#0
        BNE      |L1.260|
        LDR      r1,|L1.428|
        LDR      r0,[r1,r5,LSL #2]
        BL       ms_free_pool
        MOV      r0,#0
        LDR      r1,|L1.428|
        STR      r0,[r1,r5,LSL #2]
        MVN      r0,#0xa
        B        |L1.192|
|L1.260|
        MOV      r0,#0x55
        STRB     r0,[r6,#0]
        STR      r6,[r4,#0]
        ADD      r0,r6,#0x300
        ADD      r0,r0,#0xff
        STR      r0,[r4,#4]
        MOV      r0,#2
        STR      r0,[r4,#8]
        LDR      r0,|L1.424|
        LDR      r0,[r0,#0]  ; last_pid
        STR      r0,[r4,#0x220]
        LDR      r0,|L1.432|
        LDR      r0,[r0,#0]  ; current
        LDR      r0,[r0,#0x220]
        STR      r0,[r4,#0x224]
        LDR      r0,[r4,#0x10]
        STR      r0,[r4,#0xc]
        MOV      r0,#0
        STR      r0,[r4,#0x14]
        MOV      r0,#0
        STR      r0,[r4,#0x240]
        MOV      r0,#0
        STR      r0,[r4,#0x230]
        MOV      r0,#0
        STR      r0,[r4,#0x248]
        STR      r0,[r4,#0x244]
        MOV      r0,#0
        STR      r0,[r4,#0x250]
        STR      r0,[r4,#0x24c]
        LDR      r0,|L1.436|
        LDR      r0,[r0,#0]  ; jiffies
        STR      r0,[r4,#0x254]
        MOV      r0,#0
        STR      r0,[r4,#8]
        LDR      r0,|L1.440|
        STR      r4,[r0,#0]  ; fork_tcb
        MOV      r0,#0
        B        |L1.192|
|L1.412|
        B        |L1.144|
|L1.416|
        MVN      r0,#0xa
        B        |L1.192|
|L1.424|
        DCD      ||.bss$2||
|L1.428|
        DCD      task
|L1.432|
        DCD      current
|L1.436|
        DCD      jiffies
|L1.440|
        DCD      ||.bss$2|| + 4
        ENDP



        AREA ||.bss||, NOINIT, ALIGN=2

last_pid
||.bss$2||
        % 4
fork_tcb
        % 4


        EXPORT find_empty_and_copy_process
        EXPORT fork_tcb
        EXPORT last_pid

        IMPORT jiffies
        IMPORT current
        IMPORT ms_free_pool
        IMPORT ms_get_pool
        IMPORT task
        IMPORT ||Lib$$Request$$armlib||, WEAK

        KEEP ||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8||
||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8|| EQU 0

        ASSERT {ENDIAN} = "little"
        ASSERT {SWST} = {FALSE}
        ASSERT {NOSWST} = {TRUE}
        ASSERT {INTER} = {TRUE}
        ASSERT {ROPI} = {FALSE}
        ASSERT {RWPI} = {FALSE}
        ASSERT {NOT_SHL} = {TRUE}
        ASSERT {FULL_IEEE} = {FALSE}
        ASSERT {SHL1} = {FALSE}
        ASSERT {SHL2} = {FALSE}
        END