?? traps.c.s
字號:
; generated by ARM C Compiler, ADS1.2 [Build 805]
; commandline [-O0 -browseinfo "0xff
" -S -g+ -apcs /interwork -fk -J:cw:]
CODE32
AREA ||.text||, CODE, READONLY
out PROC
|L1.0|
MOV r1,#0
NOP
|L1.8|
LDRB r2,[r0,r1]
CMP r2,#0
BEQ |L1.44|
MOV r2,r1
ADD r1,r1,#1
LDRB r2,[r0,r2]
MOV r3,#0x2000000
STR r2,[r3,#0xc8]
B |L1.8|
|L1.44|
BX lr
ENDP
ms_int_kbd PROC
STMFD sp!,{r4,r5,lr}
MOV r0,#0x2000000
LDR r0,[r0,#0x124]
AND r4,r0,#3
MOV r0,#0x2000000
LDR r0,[r0,#0x128]
AND r5,r0,#0xff
CMP r4,#0
BNE |L1.92|
ADR r0,|L1.116|
BL out
|L1.92|
CMP r4,#1
BNE |L1.108|
ADR r0,|L1.128|
BL out
|L1.108|
LDMFD sp!,{r4,r5,lr}
BX lr
|L1.116|
DCB "Key "
DCB "down"
DCB "\r\n\0\0"
|L1.128|
DCB "Key "
DCB "up\r\n"
DCB "\0\0\0\0"
ENDP
ms_int_touch PROC
STMFD sp!,{r4-r6,lr}
MOV r0,#0x2000000
LDR r0,[r0,#0x10c]
AND r4,r0,#3
MOV r0,#0x2000000
LDR r0,[r0,#0x110]
AND r5,r0,#0xff
MOV r0,#0x2000000
LDR r0,[r0,#0x110]
MOV r0,r0,LSL #16
MOV r6,r0,LSR #24
CMP r4,#0
BNE |L1.200|
ADR r0,|L1.240|
BL out
|L1.200|
CMP r4,#1
BNE |L1.216|
ADR r0,|L1.256|
BL out
|L1.216|
CMP r4,#2
BNE |L1.232|
ADR r0,|L1.268|
BL out
|L1.232|
LDMFD sp!,{r4-r6,lr}
BX lr
|L1.240|
DCB "Touc"
DCB "h do"
DCB "wn\r\n"
DCB "\0\0\0\0"
|L1.256|
DCB "Touc"
DCB "h up"
DCB "\r\n\0\0"
|L1.268|
DCB "Touc"
DCB "h Mo"
DCB "ve\r\n"
DCB "\0\0\0\0"
ENDP
ms_int_ext0 PROC
STMFD sp!,{r4,lr}
MOV r0,#0x2000000
LDR r0,[r0,#0x44]
BIC r0,r0,#1
MOV r1,#0x2000000
STR r0,[r1,#0x44]
MOV r0,#0x2000000
LDR r0,[r0,#0x50]
MOV r4,r0,LSL #16
MOV r4,r4,LSR #16
LDR r1,|L1.448|
LDR r0,[r1,r4,LSL #2]
MOV lr,pc
BX r0
LDMFD sp!,{r4,lr}
BX lr
ENDP
ms_int_ext1 PROC
STMFD sp!,{r4,lr}
MOV r0,#0x2000000
LDR r0,[r0,#0x44]
BIC r0,r0,#2
MOV r1,#0x2000000
STR r0,[r1,#0x44]
MOV r0,#0x2000000
LDR r0,[r0,#0x50]
MOV r4,r0,LSR #16
LDR r1,|L1.452|
LDR r0,[r1,r4,LSL #2]
MOV lr,pc
BX r0
LDMFD sp!,{r4,lr}
BX lr
ENDP
ms_int_tty_tx PROC
STR lr,[sp,#-4]!
MOV r0,#0x2000000
LDR r0,[r0,#0x44]
BIC r0,r0,#4
MOV r1,#0x2000000
STR r0,[r1,#0x44]
ADR r0,|L1.456|
BL out
LDR lr,[sp],#4
BX lr
|L1.448|
DCD ||.constdata$1||
|L1.452|
DCD ||.constdata$1|| + 4
|L1.456|
DCB "uaru"
DCB "tTX\r"
DCB "\n\0\0\0"
ENDP
ms_int_tty_rx PROC
STMFD sp!,{r4,lr}
MOV r0,#0x2000000
LDR r0,[r0,#0x44]
BIC r0,r0,#8
MOV r1,#0x2000000
STR r0,[r1,#0x44]
MOV r0,#0x2000000
LDR r0,[r0,#0xcc]
AND r4,r0,#0xff
ADR r0,|L1.520|
BL out
LDMFD sp!,{r4,lr}
BX lr
|L1.520|
DCB "tty "
DCB "intp"
DCB "ut\r\n"
DCB "\0\0\0\0"
ENDP
paintPic PROC
BX lr
ENDP
ms_int_timer PROC
STR lr,[sp,#-4]!
MOV r0,#0x2000000
LDR r0,[r0,#0x44]
BIC r0,r0,#0x10
MOV r1,#0x2000000
STR r0,[r1,#0x44]
ADR r0,|L1.640|
BL out
MOV r0,#3
MOV r1,#0x2000000
STR r0,[r1,#0x100]
LDR r0,|L1.648|
LDRB r0,[r0,#0] ; lvl@ms_int_timer_0
MOV r1,#0x2000000
STR r0,[r1,#0x104]
LDR r0,|L1.648|
LDRB r0,[r0,#0] ; lvl@ms_int_timer_0
CMP r0,#0xb
BNE |L1.628|
MOV r0,#0
LDR r1,|L1.648|
STRB r0,[r1,#0] ; lvl@ms_int_timer_0
|L1.628|
BL paintPic
LDR lr,[sp],#4
BX lr
|L1.640|
DCB "time"
DCB "r\r\n\0"
|L1.648|
DCD ||.data$0||
ENDP
InterruptHandler_IRQ PROC
STMFD sp!,{r3,lr}
MOV r1,#0x2000000
LDR r1,[r1,#0x4c]
LDR r2,|L1.704|
LDR r0,[r2,r1,LSL #2]
MOV lr,pc
BX r0
LDMFD sp!,{r3,lr}
BX lr
ENDP
trap_init PROC
LDR r0,|L1.708|
LDR r1,|L1.712|
STR r0,[r1,#0] ; trap_arm_irq
BX lr
|L1.704|
DCD ||.constdata$1|| + 16
|L1.708|
DCD InterruptHandler_IRQ
|L1.712|
DCD ||.bss$2||
ENDP
AREA ||.data||, DATA, ALIGN=0
||.data$0||
||lvl@ms_int_timer_0||
DCB 0x0a
AREA ||.constdata||, DATA, READONLY, ALIGN=2
||.constdata$1||
Ext0InterruptRoutTableIRQ
DCD 0x00000000
Ext1InterruptRoutTableIRQ
DCD ms_int_kbd
DCD ms_int_touch
DCD 0x00000000
InterruptRoutTableIRQ
DCD ms_int_ext0
DCD ms_int_ext1
DCD ms_int_tty_tx
DCD ms_int_tty_rx
DCD ms_int_timer
DCD 0x00000000
AREA ||.bss||, NOINIT, ALIGN=2
trap_arm_irq
||.bss$2||
% 4
EXPORT trap_init
EXPORT InterruptHandler_IRQ
EXPORT paintPic
EXPORT out
EXPORT trap_arm_irq
EXPORT ms_int_timer
EXPORT ms_int_tty_rx
EXPORT ms_int_tty_tx
EXPORT ms_int_ext1
EXPORT ms_int_ext0
EXPORT InterruptRoutTableIRQ
EXPORT ms_int_touch
EXPORT ms_int_kbd
EXPORT Ext1InterruptRoutTableIRQ
EXPORT Ext0InterruptRoutTableIRQ
IMPORT ||Lib$$Request$$armlib||, WEAK
KEEP ||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8||
||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8|| EQU 0
ASSERT {ENDIAN} = "little"
ASSERT {SWST} = {FALSE}
ASSERT {NOSWST} = {TRUE}
ASSERT {INTER} = {TRUE}
ASSERT {ROPI} = {FALSE}
ASSERT {RWPI} = {FALSE}
ASSERT {NOT_SHL} = {TRUE}
ASSERT {FULL_IEEE} = {FALSE}
ASSERT {SHL1} = {FALSE}
ASSERT {SHL2} = {FALSE}
END
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