; generated by ARM C Compiler, ADS1.2 [Build 805]

; commandline [-O0 -browseinfo "0xff
" -S   -g+ -apcs /interwork -fk -J:cw:]
        CODE32

        AREA ||.text||, CODE, READONLY

show_task PROC
|L1.0|
        BX       lr
        ENDP

show_stat PROC
        STR      lr,[sp,#-4]!
        MOV      r2,#0
|L1.12|
        CMP      r2,#0x40
        BGE      |L1.68|
        B        |L1.32|
|L1.24|
        ADD      r2,r2,#1
        B        |L1.12|
|L1.32|
        LDR      r0,|L1.488|
        LDR      r0,[r0,r2,LSL #2]
        CMP      r0,#0
        BEQ      |L1.64|
        LDR      r0,|L1.488|
        LDR      r1,[r0,r2,LSL #2]
        MOV      r0,r2
        BL       show_task
|L1.64|
        B        |L1.24|
|L1.68|
        LDR      lr,[sp],#4
        BX       lr
        ENDP

schedule PROC
        STMFD    sp!,{r3-r7,lr}
        LDR      r4,|L1.492|
|L1.84|
        LDR      r0,|L1.488|
        CMP      r4,r0
        BLS      |L1.256|
        B        |L1.108|
|L1.100|
        SUB      r4,r4,#4
        B        |L1.84|
|L1.108|
        LDR      r0,[r4,#0]
        CMP      r0,#0
        BEQ      |L1.252|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#0x240]
        CMP      r0,#0
        BEQ      |L1.192|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#0x240]
        LDR      r1,|L1.496|
        LDR      r1,[r1,#0]  ; jiffies
        CMP      r0,r1
        BGE      |L1.192|
        LDR      r1,[r4,#0]
        ADD      r0,r1,#0x14
        LDR      r1,[r1,#0x14]
        ORR      r1,r1,#0x2000
        STR      r1,[r0,#0]
        MOV      r0,#0
        LDR      r1,[r4,#0]
        STR      r0,[r1,#0x240]
|L1.192|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#0x14]
        LDR      r1,[r4,#0]
        LDR      r1,[r1,#0x218]
        BIC      r1,r1,#0x40000
        BIC      r1,r1,#0x100
        BICS     r0,r0,r1
        BEQ      |L1.252|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#8]
        CMP      r0,#1
        BNE      |L1.252|
        MOV      r0,#0
        LDR      r1,[r4,#0]
        STR      r0,[r1,#8]
|L1.252|
        B        |L1.100|
|L1.256|
        NOP      
|L1.260|
        NOP      
        MVN      r6,#0
        MOV      r7,#0
        MOV      r5,#0x40
        LDR      r4,|L1.500|
        NOP      
|L1.284|
        SUB      r0,r5,#1
        MOVS     r5,r0
        BEQ      |L1.368|
        SUB      r0,r4,#4
        MOV      r4,r0
        LDR      r0,[r0,#0]
        CMP      r0,#0
        BNE      |L1.320|
        B        |L1.284|
|L1.320|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#8]
        CMP      r0,#0
        BNE      |L1.364|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#0xc]
        CMP      r0,r6
        BLE      |L1.364|
        LDR      r0,[r4,#0]
        LDR      r6,[r0,#0xc]
        MOV      r7,r5
|L1.364|
        B        |L1.284|
|L1.368|
        CMP      r6,#0
        BEQ      |L1.380|
        B        |L1.456|
|L1.380|
        LDR      r4,|L1.492|
|L1.384|
        LDR      r0,|L1.488|
        CMP      r4,r0
        BLS      |L1.452|
        B        |L1.408|
|L1.400|
        SUB      r4,r4,#4
        B        |L1.384|
|L1.408|
        LDR      r0,[r4,#0]
        CMP      r0,#0
        BEQ      |L1.448|
        LDR      r0,[r4,#0]
        LDR      r0,[r0,#0x10]
        LDR      r1,[r4,#0]
        LDR      r1,[r1,#0xc]
        ADD      r0,r0,r1,ASR #1
        LDR      r1,[r4,#0]
        STR      r0,[r1,#0xc]
|L1.448|
        B        |L1.400|
|L1.452|
        B        |L1.260|
|L1.456|
        LDR      r0,|L1.488|
        LDR      r0,[r0,r7,LSL #2]
        LDR      r1,|L1.504|
        STR      r0,[r1,#0]  ; next
        BL       switch_to
        LDMFD    sp!,{r3-r7,lr}
        BX       lr
        ENDP

sched_init PROC
        BX       lr
|L1.488|
        DCD      task
|L1.492|
        DCD      task + 252
|L1.496|
        DCD      ||.bss$2|| + 4
|L1.500|
        DCD      task + 256
|L1.504|
        DCD      ||.bss$2||
        ENDP



        AREA ||.data||, DATA, ALIGN=2

||.data$0||
task0
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x0000000f
        DCD      0x0000000f
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        %        496
        DCD      0x00000000
        DCD      0x00000000
        DCD      0xffffffff
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCW      0x0000
        DCW      0x0000
        DCW      0x0000
        DCW      0x0000
        DCW      0x0000
        DCW      0x0000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCD      0x00000000
        DCW      0x0000
        DCB      0x00,0x00
        DCD      0x00000000
current
        DCD      task0
task
        DCD      task0
        %        252


        AREA ||.bss||, NOINIT, ALIGN=2

next
||.bss$2||
        % 4
jiffies
        % 4
startup_time
        % 4


        EXPORT sched_init
        EXPORT schedule
        EXPORT show_stat
        EXPORT show_task
        EXPORT startup_time
        EXPORT jiffies
        EXPORT next
        EXPORT task
        EXPORT current
        EXPORT task0

        IMPORT switch_to
        IMPORT ||Lib$$Request$$armlib||, WEAK

        KEEP ||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8||
||BuildAttributes$$THUMB_ISAv1$M$PE$A:L22$X:L11$S22$IW$USESV6$~STKCKD$USESV7$~SHL$OSPACE$PRES8|| EQU 0

        ASSERT {ENDIAN} = "little"
        ASSERT {SWST} = {FALSE}
        ASSERT {NOSWST} = {TRUE}
        ASSERT {INTER} = {TRUE}
        ASSERT {ROPI} = {FALSE}
        ASSERT {RWPI} = {FALSE}
        ASSERT {NOT_SHL} = {TRUE}
        ASSERT {FULL_IEEE} = {FALSE}
        ASSERT {SHL1} = {FALSE}
        ASSERT {SHL2} = {FALSE}
        END