;; MShowTec - www.mshowtec.com
;; msLinux snds.s ver1.0
;; 20051221 lmjx create limiao@mshowtec.com
;;
;;

;;  MSLINUX_SNDS_S

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F 

MASK_MODE		EQU		0x0000003F
MODE_SVC32		EQU		0x00000013

I_BIT           EQU     0x80 ; when I bit is set, IRQ is disabled
F_BIT           EQU     0x40 ; when F bit is set, FIQ is disabled


ASIC_BASE  	 	EQU 	0x02000000


;SYSTEM MANAGER REGISTERS 
ARM7_SYSCFG	    EQU 	(ASIC_BASE+0x00)
ARM7_MEMMAP  	EQU 	(ASIC_BASE+0x04)


; INT Controller registers
ARM7_INTMODE 	EQU 	(ASIC_BASE+0x40)
ARM7_INTPEND 	EQU 	(ASIC_BASE+0x44)
ARM7_INTMASK 	EQU 	(ASIC_BASE+0x48)
ARM7_INTOFFSET  EQU 	(ASIC_BASE+0x4c)
ARM7_INTROUTER  EQU 	(ASIC_BASE+0x50)

; Timer Registers
ARM7_TMOD		EQU		(ASIC_BASE+0x80)
ARM7_TDATA		EQU		(ASIC_BASE+0x84)
ARM7_TRELOAD	EQU		(ASIC_BASE+0x88)
ARM7_TCNT		EQU		(ASIC_BASE+0x8c)

;UART Registers
ARM7_UCON		EQU		(ASIC_BASE+0xc0)
ARM7_USTAT		EQU		(ASIC_BASE+0xc4)
ARM7_UTXBUF		EQU		(ASIC_BASE+0xc8)
ARM7_URXBUF		EQU		(ASIC_BASE+0xcc)

;DEV Registers
ARM7_LCDADDR	EQU		(ASIC_BASE+0x100)
ARM7_LCDDATA	EQU		(ASIC_BASE+0x104)

ARM7_TOUCHCON	EQU		(ASIC_BASE+0x108)
ARM7_TOUCHSTATE	EQU		(ASIC_BASE+0x10c)
ARM7_TOUCHBUF	EQU		(ASIC_BASE+0x110)

ARM7_KBDCON		EQU		(ASIC_BASE+0x120)
ARM7_KBDSTATE	EQU		(ASIC_BASE+0x124)
ARM7_KBDBUF		EQU		(ASIC_BASE+0x128)

       END