;; Cirrus EP9312 "Maverick" ARM floating point co-processor description.;; Copyright (C) 2003, 2004, 2005 Free Software Foundation, Inc.;; Contributed by Red Hat.;; Written by Aldy Hernandez (aldyh@redhat.com);; This file is part of GCC.;; GCC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 2, or (at your option);; any later version.;; GCC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GCC; see the file COPYING.  If not, write to;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,;; Boston, MA 02110-1301, USA.; Cirrus types for invalid insn combinations; not		Not a cirrus insn; normal	Any Cirrus insn not covered by the special cases below; double	cfldrd, cfldr64, cfstrd, cfstr64; compare	cfcmps, cfcmpd, cfcmp32, cfcmp64; move		cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not"))(define_insn "cirrus_adddi3"  [(set (match_operand:DI          0 "cirrus_fp_register" "=v")	(plus:DI (match_operand:DI 1 "cirrus_fp_register"  "v")		 (match_operand:DI 2 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfadd64%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_addsi3"  [(set (match_operand:SI          0 "cirrus_fp_register" "=v")	(plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")		 (match_operand:SI 2 "cirrus_fp_register" "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfadd32%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_addsf3"  [(set (match_operand:SF          0 "cirrus_fp_register" "=v")	(plus:SF (match_operand:SF 1 "cirrus_fp_register" "v")		 (match_operand:SF 2 "cirrus_fp_register" "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfadds%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_adddf3"  [(set (match_operand:DF          0 "cirrus_fp_register" "=v")	(plus:DF (match_operand:DF 1 "cirrus_fp_register" "v")		 (match_operand:DF 2 "cirrus_fp_register" "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfaddd%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "cirrus_subdi3"  [(set (match_operand:DI           0 "cirrus_fp_register" "=v")	(minus:DI (match_operand:DI 1 "cirrus_fp_register"  "v")		  (match_operand:DI 2 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfsub64%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_subsi3_insn"  [(set (match_operand:SI           0 "cirrus_fp_register" "=v")	(minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")		  (match_operand:SI 2 "cirrus_fp_register" "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfsub32%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_subsf3"  [(set (match_operand:SF           0 "cirrus_fp_register" "=v")	(minus:SF (match_operand:SF 1 "cirrus_fp_register"  "v")		  (match_operand:SF 2 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfsubs%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_subdf3"  [(set (match_operand:DF           0 "cirrus_fp_register" "=v")	(minus:DF (match_operand:DF 1 "cirrus_fp_register" "v")		  (match_operand:DF 2 "cirrus_fp_register" "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfsubd%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_mulsi3"  [(set (match_operand:SI          0 "cirrus_fp_register" "=v")	(mult:SI (match_operand:SI 2 "cirrus_fp_register"  "v")		 (match_operand:SI 1 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfmul32%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "muldi3"  [(set (match_operand:DI          0 "cirrus_fp_register" "=v")	(mult:DI (match_operand:DI 2 "cirrus_fp_register"  "v")		 (match_operand:DI 1 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfmul64%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_dmult")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_mulsi3addsi"  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")	(plus:SI	  (mult:SI (match_operand:SI 1 "cirrus_fp_register"  "v")		   (match_operand:SI 2 "cirrus_fp_register"  "v"))	  (match_operand:SI          3 "cirrus_fp_register"  "0")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfmac32%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")]);; Cirrus SI multiply-subtract(define_insn "*cirrus_mulsi3subsi"  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")	(minus:SI	  (match_operand:SI          1 "cirrus_fp_register"  "0")	  (mult:SI (match_operand:SI 2 "cirrus_fp_register"  "v")		   (match_operand:SI 3 "cirrus_fp_register"  "v"))))]  "0 && TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfmsc32%?\\t%V0, %V2, %V3"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_mulsf3"  [(set (match_operand:SF          0 "cirrus_fp_register" "=v")	(mult:SF (match_operand:SF 1 "cirrus_fp_register"  "v")		 (match_operand:SF 2 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfmuls%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_farith")   (set_attr "cirrus" "normal")])(define_insn "*cirrus_muldf3"  [(set (match_operand:DF          0 "cirrus_fp_register" "=v")	(mult:DF (match_operand:DF 1 "cirrus_fp_register"  "v")		 (match_operand:DF 2 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfmuld%?\\t%V0, %V1, %V2"  [(set_attr "type" "mav_dmult")   (set_attr "cirrus" "normal")])(define_insn "cirrus_ashl_const"  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")	(ashift:SI (match_operand:SI 1 "cirrus_fp_register"  "v")		   (match_operand:SI 2 "cirrus_shift_const"  "")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfsh32%?\\t%V0, %V1, #%s2"  [(set_attr "cirrus" "normal")])(define_insn "cirrus_ashiftrt_const"  [(set (match_operand:SI	       0 "cirrus_fp_register" "=v")	(ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register"  "v")		     (match_operand:SI 2 "cirrus_shift_const"  "")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfsh32%?\\t%V0, %V1, #-%s2"  [(set_attr "cirrus" "normal")])(define_insn "cirrus_ashlsi3"  [(set (match_operand:SI            0 "cirrus_fp_register" "=v")	(ashift:SI (match_operand:SI 1 "cirrus_fp_register"  "v")		   (match_operand:SI 2 "register_operand"    "r")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0"  "cfrshl32%?\\t%V1, %V0, %s2"  [(set_attr "cirrus" "normal")])(define_insn "ashldi3_cirrus"  [(set (match_operand:DI            0 "cirrus_fp_register" "=v")	(ashift:DI (match_operand:DI 1 "cirrus_fp_register"  "v")		   (match_operand:SI 2 "register_operand"    "r")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfrshl64%?\\t%V1, %V0, %s2"  [(set_attr "cirrus" "normal")])(define_insn "cirrus_ashldi_const"  [(set (match_operand:DI            0 "cirrus_fp_register" "=v")	(ashift:DI (match_operand:DI 1 "cirrus_fp_register"  "v")		   (match_operand:SI 2 "cirrus_shift_const"  "")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfsh64%?\\t%V0, %V1, #%s2"  [(set_attr "cirrus" "normal")])(define_insn "cirrus_ashiftrtdi_const"  [(set (match_operand:DI            0 "cirrus_fp_register" "=v")	(ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register"  "v")		     (match_operand:SI 2 "cirrus_shift_const"  "")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfsh64%?\\t%V0, %V1, #-%s2"  [(set_attr "cirrus" "normal")])(define_insn "*cirrus_absdi2"  [(set (match_operand:DI         0 "cirrus_fp_register" "=v")	(abs:DI (match_operand:DI 1 "cirrus_fp_register"  "v")))]  "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"  "cfabs64%?\\t%V0, %V1"  [(set_attr "cirrus" "normal")]);; This doesn't really clobber ``cc''.  Fixme: aldyh.  (define_insn "*cirrus_negdi2"