+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                            ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path                                                                 ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------------------+
; full_featured.bdf                ; yes             ; D:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/full_featured.bdf       ;
; altera_vhdl_support.vhd          ; yes             ; D:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/altera_vhdl_support.vhd ;
; full_1c20.vhd                    ; yes             ; D:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/full_1c20.vhd           ;
; bswap_cpu.vhd                    ; yes             ; D:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/bswap_cpu.vhd           ;
; button_pio.vhd                   ; yes             ; D:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/button_pio.vhd          ;
+----------------------------------+-----------------+----------------------------------------------------------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sat Jun 11 19:38:23 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off full_featured -c full_featured
Info: Found 1 design units, including 1 entities, in source file full_featured.bdf
    Info: Found entity 1: full_featured
Info: Found 2 design units, including 0 entities, in source file altera_vhdl_support.vhd
    Info: Found design unit 1: altera_vhdl_support_lib
    Info: Found design unit 2: altera_vhdl_support_lib-body
Info: Using design file full_1c20.vhd, which is not specified as a design file for the current project, but contains definitions for 60 design units and 30 entities in project
    Info: Found design unit 1: bswap_cpu_s1_arbitrator-europa
    Info: Found design unit 2: button_pio_s1_arbitrator-europa
    Info: Found design unit 3: cpu_jtag_debug_module_arbitrator-europa
    Info: Found design unit 4: cpu_custom_instruction_master_arbitrator-europa
    Info: Found design unit 5: cpu_data_master_arbitrator-europa
    Info: Found design unit 6: cpu_instruction_master_arbitrator-europa
    Info: Found design unit 7: dma_control_port_slave_arbitrator-europa
    Info: Found design unit 8: dma_read_master_arbitrator-europa
    Info: Found design unit 9: dma_write_master_arbitrator-europa
    Info: Found design unit 10: epcs_controller_epcs_control_port_arbitrator-europa
    Info: Found design unit 11: ext_ram_bus_avalon_slave_arbitrator-europa
    Info: Found design unit 12: ext_ram_bus_bridge_arbitrator-europa
    Info: Found design unit 13: high_res_timer_s1_arbitrator-europa
    Info: Found design unit 14: jtag_uart_avalon_jtag_slave_arbitrator-europa
    Info: Found design unit 15: lcd_display_control_slave_arbitrator-europa
    Info: Found design unit 16: led_pio_s1_arbitrator-europa
    Info: Found design unit 17: reconfig_request_pio_s1_arbitrator-europa
    Info: Found design unit 18: sdram_s1_arbitrator-europa
    Info: Found design unit 19: seven_seg_pio_s1_arbitrator-europa
    Info: Found design unit 20: sys_clk_timer_s1_arbitrator-europa
    Info: Found design unit 21: sysid_control_slave_arbitrator-europa
    Info: Found design unit 22: uart1_s1_arbitrator-europa
    Info: Found design unit 23: full_1c20-europa
    Info: Found design unit 24: ext_flash_lane0_module-europa
    Info: Found design unit 25: ext_flash-europa
    Info: Found design unit 26: ext_ram_lane0_module-europa
    Info: Found design unit 27: ext_ram_lane1_module-europa
    Info: Found design unit 28: ext_ram_lane2_module-europa
    Info: Found design unit 29: ext_ram_lane3_module-europa
    Info: Found design unit 30: ext_ram-europa
    Info: Found entity 1: bswap_cpu_s1_arbitrator
    Info: Found entity 2: button_pio_s1_arbitrator
    Info: Found entity 3: cpu_jtag_debug_module_arbitrator
    Info: Found entity 4: cpu_custom_instruction_master_arbitrator
    Info: Found entity 5: cpu_data_master_arbitrator
    Info: Found entity 6: cpu_instruction_master_arbitrator
    Info: Found entity 7: dma_control_port_slave_arbitrator
    Info: Found entity 8: dma_read_master_arbitrator
    Info: Found entity 9: dma_write_master_arbitrator
    Info: Found entity 10: epcs_controller_epcs_control_port_arbitrator
    Info: Found entity 11: ext_ram_bus_avalon_slave_arbitrator
    Info: Found entity 12: ext_ram_bus_bridge_arbitrator
    Info: Found entity 13: high_res_timer_s1_arbitrator
    Info: Found entity 14: jtag_uart_avalon_jtag_slave_arbitrator
    Info: Found entity 15: lcd_display_control_slave_arbitrator
    Info: Found entity 16: led_pio_s1_arbitrator
    Info: Found entity 17: reconfig_request_pio_s1_arbitrator
    Info: Found entity 18: sdram_s1_arbitrator
    Info: Found entity 19: seven_seg_pio_s1_arbitrator
    Info: Found entity 20: sys_clk_timer_s1_arbitrator
    Info: Found entity 21: sysid_control_slave_arbitrator
    Info: Found entity 22: uart1_s1_arbitrator
    Info: Found entity 23: full_1c20
    Info: Found entity 24: ext_flash_lane0_module
    Info: Found entity 25: ext_flash
    Info: Found entity 26: ext_ram_lane0_module
    Info: Found entity 27: ext_ram_lane1_module
    Info: Found entity 28: ext_ram_lane2_module
    Info: Found entity 29: ext_ram_lane3_module
    Info: Found entity 30: ext_ram
Info: Using design file bswap_cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bswap_cpu-europa
    Info: Found entity 1: bswap_cpu
Info: Using design file button_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: button_pio-europa
    Info: Found entity 1: button_pio
Warning: FLEXlm software error: Future license file format or misspelling in license file  The file was issued for a later version of FLEXlm than this  program understands. Feature:       6AF7_00A2 License path:  D:/altera/license_all.dat FLEXlm error:  -90,313 For further information, refer to the FLEXlm End User Manual, available at "www.macrovision.com".
Error: Can't open encrypted VHDL or Verilog HDL file "D:/altera/kits/nios2/examples/vhdl/niosII_cyclone_1c20/full_featured/cpu.vhd" -- current license file does not contain a valid license for encrypted file
Error: Node instance "the_cpu" instantiates undefined entity "cpu"
Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning
    Error: Processing ended: Sat Jun 11 19:38:30 2005
    Error: Elapsed time: 00:00:08