?? regs54xx.h
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#define XCEA15_SZ 1
#define XCEA14 14
#define XCEA14_SZ 1
#define XCEA13 13
#define XCEA13_SZ 1
#define XCEA12 12
#define XCEA12_SZ 1
#define XCEA11 11
#define XCEA11_SZ 1
#define XCEA10 10
#define XCEA10_SZ 1
#define XCEA9 9
#define XCEA9_SZ 1
#define XCEA8 8
#define XCEA8_SZ 1
#define XCEA7 7
#define XCEA7_SZ 1
#define XCEA6 6
#define XCEA6_SZ 1
#define XCEA5 5
#define XCEA5_SZ 1
#define XCEA4 4
#define XCEA4_SZ 1
#define XCEA3 3
#define XCEA3_SZ 1
#define XCEA2 2
#define XCEA2_SZ 1
#define XCEA1 1
#define XCEA1_SZ 1
#define XCEA0 0
#define XCEA0_SZ 1
/*-------------------------------------------------------------------*/
/* Define bit fields for Transmit Channel Enable Register Partition B*/
/*-------------------------------------------------------------------*/
#define XCEB15 15
#define XCEB15_SZ 1
#define XCEB14 14
#define XCEB14_SZ 1
#define XCEB13 13
#define XCEB13_SZ 1
#define XCEB12 12
#define XCEB12_SZ 1
#define XCEB11 11
#define XCEB11_SZ 1
#define XCEB10 10
#define XCEB10_SZ 1
#define XCEB9 9
#define XCEB9_SZ 1
#define XCEB8 8
#define XCEB8_SZ 1
#define XCEB7 7
#define XCEB7_SZ 1
#define XCEB6 6
#define XCEB6_SZ 1
#define XCEB5 5
#define XCEB5_SZ 1
#define XCEB4 4
#define XCEB4_SZ 1
#define XCEB3 3
#define XCEB3_SZ 1
#define XCEB2 2
#define XCEB2_SZ 1
#define XCEB1 1
#define XCEB1_SZ 1
#define XCEB0 0
#define XCEB0_SZ 1
/*-------------------------------------------------------------------*/
/* Define bit fields for Pin Control Register */
/*-------------------------------------------------------------------*/
#define XIOEN 13
#define XIOEN_SZ 1
#define RIOEN 12
#define RIOEN_SZ 1
#define FSXM 11
#define FSXM_SZ 1
#define FSRM 10
#define FSRM_SZ 1
#define CLKXM 9
#define CLKXM_SZ 1
#define CLKRM 8
#define CLKRM_SZ 1
#define CLKS_STAT 6
#define CLKS_STAT_SZ 1
#define DX_STAT 5
#define DX_STAT_SZ 1
#define DR_STAT 4
#define DR_STAT_SZ 1
#define FSXP 3
#define FSXP_SZ 1
#define FSRP 2
#define FSRP_SZ 1
#define CLKXP 1
#define CLKXP_SZ 1
#define CLKRP 0
#define CLKRP_SZ 1
/*******************************/
/* Register Definition MCBSP */
/*******************************/
/*----------------PORT----------------------------------|-2--|--1--|-0--|*/
//Added by T. kyiamah
#define SPCR1_ADDR(port) (port ? 0x49 : 0x39)
#define SPCR2_ADDR(port) (port ? 0x49 : 0x39)
#define SPSA_ADDR(port) (port ? 0x48 : 0x38)
#define SPSD_ADDR(port) (port ? 0x49 : 0x39)
#define DRR2_ADDR(port) (port ? 0x40 : 0x20)
#define DRR1_ADDR(port) (port ? 0x41 : 0x21)
#define DXR2_ADDR(port) (port ? 0x42 : 0x22)
#define DXR1_ADDR(port) (port ? 0x43 : 0x23)
#define MCBSP_ACCSUB_ADDR(port) (port ? 0x49 : 0x39)
#define SPCR1_SUBADDR 0x00
#define SPCR2_SUBADDR 0x01
#define RCR1_SUBADDR 0x02
#define RCR2_SUBADDR 0x03
#define XCR1_SUBADDR 0x04
#define XCR2_SUBADDR 0x05
#define SRGR1_SUBADDR 0x06
#define SRGR2_SUBADDR 0x07
#define MCR1_SUBADDR 0x08
#define MCR2_SUBADDR 0x09
#define RCERA_SUBADDR 0x0A
#define RCERB_SUBADDR 0x0B
#define XCERA_SUBADDR 0x0C
#define XCERB_SUBADDR 0x0D
#define PCR_SUBADDR 0x0E
/*****************DMA Registers, Bits, Bitfields*****************/
/*----------------------------------------------------------------------------*/
/* Define bit fields for DMPRE Register */
/*----------------------------------------------------------------------------*/
#define DMA_FREE 15
#define DMA_FREE_SZ 1
#define DPRC 8
#define DPRC_SZ 6
#define DPRC5 13
#define DPRC5_SZ 1
#define DPRC4 12
#define DPRC4_SZ 1
#define DPRC3 11
#define DPRC3_SZ 1
#define DPRC2 10
#define DPRC2_SZ 1
#define DPRC1 9
#define DPRC1_SZ 1
#define DPRC0 8
#define DPRC0_SZ 1
#define INTSEL 6
#define INTSEL_SZ 2
#define DE 0
#define DE_SZ 6
#define DE5 5
#define DE5_SZ 1
#define DE4 4
#define DE4_SZ 1
#define DE3 3
#define DE3_SZ 1
#define DE2 2
#define DE2_SZ 1
#define DE1 1
#define DE1_SZ 1
#define DE0 0
#define DE0_SZ 1
/*----------------------------------------------------------------------------*/
/* Define bit fields for DMSEFCn Register */
/*----------------------------------------------------------------------------*/
#define FRAMECOUNT 0
#define FRAMECOUNT_SZ 8
#define DSYN 12
#define DSYN_SZ 4
#define DLBW 11
#define DLBW_SZ 1
/*----------------------------------------------------------------------------*/
/* Define bit fields for DMMRCn Register */
/*----------------------------------------------------------------------------*/
#define AUTOINIT 15
#define AUTOINIT_SZ 1
#define DINM 14
#define DINM_SZ 1
#define IMOD 13
#define IMOD_SZ 1
#define CTMOD 12
#define CTMOD_SZ 1
#define SIND 8
#define SIND_SZ 3
#define DMS 6
#define DMS_SZ 2
#define DIND 2
#define DIND_SZ 3
#define DMD 0
#define DMD_SZ 2
/****************************/
/* Register Definition DMA */
/****************************/
#define DMPREC *(volatile unsigned int*)0x54
#define DMPRE_ADDR 0x54
#define DMSBA_ADDR 0x55
#define DMSAI_ADDR 0x56
#define DMA_ACCSUB_ADDR 0x57
#define DMSRC_SUBADDR 0x00
#define DMDST_SUBADDR 0x01
#define DMCTR_SUBADDR 0x02
#define DMSEFC_SUBADDR 0x03
#define DMMCR_SUBADDR 0x04
#define DMSRCP_SUBADDR 0x1E
#define DMDSTP_SUBADDR 0x1F
#define DMIDX0_SUBADDR 0x20
#define DMIDX1_SUBADDR 0x21
#define DMFRI0_SUBADDR 0x22
#define DMFRI1_SUBADDR 0x23
#define DMGSA_SUBADDR 0x24
#define DMGDA_SUBADDR 0x25
#define DMGCR_SUBADDR 0x26
#define DMGFR_SUBADDR 0x27
/******************************************************************/
/* Subregister Read / Write */
/******************************************************************/
#define MCBSP_SUBREG_WRITE(port, subaddr, value) \
((REG_WRITE(SPSA_ADDR(port), subaddr)), (REG_WRITE(MCBSP_ACCSUB_ADDR(port), value)))
#define MCBSP_SUBREG_READ(port, subaddr) \
((REG_WRITE(SPSA_ADDR(port), subaddr)), (REG_READ(MCBSP_ACCSUB_ADDR(port))))
#define DMA_SUBREG_WRITE(chan, subaddr, value) \
((subaddr>=0x1E) ?\
(REG_WRITE(DMSBA_ADDR, (subaddr)), REG_WRITE(DMSAI_ADDR, value))\
:(REG_WRITE(DMSBA_ADDR, (chan*5+subaddr)), REG_WRITE(DMSAI_ADDR, value)) )
#define DMA_SUBREG_READ(chan, subaddr) \
((subaddr>=0x1E) ?\
(REG_WRITE(DMSBA_ADDR, (subaddr)), REG_READ(DMSAI_ADDR))\
:(REG_WRITE(DMSBA_ADDR, (chan*5+subaddr)), REG_READ(DMSAI_ADDR)) )
/******************************************************************/
/* Subregister Bit Field Read / Write */
/******************************************************************/
#define MCBSP_SUBREG_BITWRITE(port, subaddr, bit, size, value) \
REG_WRITE(MCBSP_ACCSUB_ADDR(port), (((REG_WRITE(SPSA_ADDR(port), subaddr), REG_READ(MCBSP_ACCSUB_ADDR(port))) & ~CREATE_FIELD(bit, size)) | ((value) << (bit)) ) )
#define MCBSP_SUBREG_BITREAD(port, subaddr, bit, size) \
(unsigned int) (REG_WRITE(SPSA_ADDR(port), subaddr), (REG_READ(MCBSP_ACCSUB_ADDR(port)) & CREATE_FIELD(bit, size)) >>(bit) )
#define DMA_SUBREG_BITWRITE(chan, subaddr, bit, size, value) \
((subaddr>=0x1E) ?\
(REG_WRITE(DMSBA_ADDR, (((REG_WRITE(DMSBA_ADDR, subaddr), REG_READ(DMA_ACCSUB_ADDR)) & ~CREATE_FIELD(bit, size)) | ((value) << (bit)) ) ) )\
:(REG_WRITE(DMSBA_ADDR, (((REG_WRITE(DMSBA_ADDR, (chan)), (REG_READ(DMA_ACCSUB_ADDR) & CREATE_FIELD(bit, size))>>(bit)))))))
#define DMA_SUBREG_BITREAD(chan, subaddr, bit, size) \
((subaddr>=0x1E) ?\
((unsigned int) (REG_WRITE(DMSBA_ADDR, subaddr), (REG_READ(DMA_ACCSUB_ADDR) & CREATE_FIELD(bit, size)) >>(bit) ))\
:((unsigned int) (REG_WRITE(DMSBA_ADDR, (chan*5+subaddr)), (REG_READ(DMA_ACCSUB_ADDR) & CREATE_FIELD(bit, size)) >>(bit) )))
/* | The following part of 54XXregs.h was not needed for my purposes. */
/* | It has already been included in the regs.h I have received from */
/* \/ Karen Baldwin (?) some time ago. */
/********************/
/* Interrupt Vectors*/
/********************/
#define BASE_VEC_ADR 0x80
#define RESET_VEC 0x0
#define NMI_VEC 4
#define SINT17_VEC 8
#define SINT18_VEC 12
#define SINT19_VEC 16
#define SINT20_VEC 20
#define SINT21_VEC 24
#define SINT22_VEC 28
#define SINT23_VEC 32
#define SINT24_VEC 36
#define SINT25_VEC 40
#define SINT26_VEC 44
#define SINT27_VEC 48
#define SINT28_VEC 52
#define SINT29_VEC 56
#define SINT30_VEC 60
#define INT0_VEC 64
#define INT1_VEC 68
#define INT2_VEC 72
#define TINT0_VEC 76
#define RINT0_VEC 80
#define XINT0_VEC 84
#define DMAC0_VEC 88
#define TINT1_VEC 92
#define INT3_VEC 96
#define HPI_VEC 100
#define RINT1_VEC 104
#define XINT1_VEC 108
#define DMAC2_VEC 104
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