?? stm32f10x_usart.s79
字號:
//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:34 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_usart.c /
// Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_usart.c" -D /
// VECT_TAB_FLASH -lcN "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" /
// -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" -o /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 /
// --no_cse --no_unroll --no_inline --no_code_motion /
// --no_tbaa --no_clustering --no_scheduling --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\" -I "C:\David /
// JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\include\" -I /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\..\FWLib\inc\" -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0\arm\INC\" /
// List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
// f10x_usart.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_usart
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable12 EQU 0
??DataTable19 EQU 0
??DataTable2 EQU 0
??DataTable20 EQU 0
??DataTable21 EQU 0
??DataTable23 EQU 0
??DataTable24 EQU 0
??DataTable25 EQU 0
??DataTable26 EQU 0
??DataTable27 EQU 0
??DataTable28 EQU 0
??DataTable29 EQU 0
??DataTable3 EQU 0
??DataTable30 EQU 0
??DataTable31 EQU 0
??DataTable33 EQU 0
??DataTable34 EQU 0
??DataTable35 EQU 0
??DataTable36 EQU 0
??DataTable38 EQU 0
??DataTable4 EQU 0
??DataTable40 EQU 0
??DataTable41 EQU 0
??DataTable42 EQU 0
??DataTable43 EQU 0
??DataTable44 EQU 0
??DataTable45 EQU 0
??DataTable46 EQU 0
??DataTable5 EQU 0
??DataTable6 EQU 0
??DataTable7 EQU 0
??DataTable8 EQU 0
??DataTable9 EQU 0
MULTWEAK ??RCC_APB1PeriphResetCmd??rT
MULTWEAK ??RCC_APB2PeriphResetCmd??rT
MULTWEAK ??RCC_GetClocksFreq??rT
MULTWEAK ??assert_failed??rT
PUBLIC USART_ClearFlag
PUBLIC USART_ClearITPendingBit
PUBLIC USART_Cmd
PUBLIC USART_DMACmd
PUBLIC USART_DeInit
PUBLIC USART_GetFlagStatus
PUBLIC USART_GetITStatus
PUBLIC USART_HalfDuplexCmd
PUBLIC USART_ITConfig
PUBLIC USART_Init
PUBLIC USART_IrDACmd
PUBLIC USART_IrDAConfig
PUBLIC USART_LINBreakDetectLengthConfig
PUBLIC USART_LINCmd
PUBLIC USART_ReceiveData
PUBLIC USART_ReceiverWakeUpCmd
PUBLIC USART_SendBreak
PUBLIC USART_SendData
PUBLIC USART_SetAddress
PUBLIC USART_SetGuardTime
PUBLIC USART_SetPrescaler
PUBLIC USART_SmartCardCmd
PUBLIC USART_SmartCardNACKCmd
PUBLIC USART_StructInit
PUBLIC USART_WakeUpConfig
RCC_APB1PeriphResetCmd SYMBOL "RCC_APB1PeriphResetCmd"
RCC_APB2PeriphResetCmd SYMBOL "RCC_APB2PeriphResetCmd"
RCC_GetClocksFreq SYMBOL "RCC_GetClocksFreq"
assert_failed SYMBOL "assert_failed"
??RCC_APB1PeriphResetCmd??rT SYMBOL "??rT", RCC_APB1PeriphResetCmd
??RCC_APB2PeriphResetCmd??rT SYMBOL "??rT", RCC_APB2PeriphResetCmd
??RCC_GetClocksFreq??rT SYMBOL "??rT", RCC_GetClocksFreq
??assert_failed??rT SYMBOL "??rT", assert_failed
EXTERN RCC_APB1PeriphResetCmd
EXTERN RCC_APB2PeriphResetCmd
EXTERN RCC_GetClocksFreq
EXTERN assert_failed
RSEG CODE:CODE:NOROOT(2)
THUMB
USART_DeInit:
PUSH {LR}
LDR.N R1,??USART_DeInit_0 ;; 0x40004400
CMP R0,R1
BEQ.N ??USART_DeInit_1
LDR.N R1,??USART_DeInit_0+0x4 ;; 0x40004800
CMP R0,R1
BEQ.N ??USART_DeInit_2
LDR.N R1,??DataTable11 ;; 0x40013800
CMP R0,R1
BNE.N ??USART_DeInit_3
??USART_DeInit_4:
MOVS R1,#+1
MOVS R0,#+16384
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+16384
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
B.N ??USART_DeInit_3
??USART_DeInit_1:
MOVS R1,#+1
MOVS R0,#+131072
_BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+131072
_BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
B.N ??USART_DeInit_3
??USART_DeInit_2:
MOVS R1,#+1
MOVS R0,#+262144
_BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+262144
_BLF RCC_APB1PeriphResetCmd,??RCC_APB1PeriphResetCmd??rT
??USART_DeInit_3:
POP {PC} ;; return
Nop
DATA
??USART_DeInit_0:
DC32 0x40004400
DC32 0x40004800
RSEG CODE:CODE:NOROOT(2)
THUMB
USART_Init:
PUSH {R4-R6,LR}
SUB SP,SP,#+20
MOVS R4,R0
MOVS R6,R1
MOVS R5,#+0
MOVS R0,#+0
MOVS R1,#+0
MOVS R2,#+0
LDR R3,[R6, #+0]
CMP R3,#+0
BEQ.N ??USART_Init_0
LDR R0,[R6, #+0]
LDR.N R1,??USART_Init_1 ;; 0x44aa21
CMP R0,R1
BCC.N ??USART_Init_2
??USART_Init_0:
MOVS R1,#+135
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_2:
LDRH R0,[R6, #+4]
CMP R0,#+0
BEQ.N ??USART_Init_3
LDRH R0,[R6, #+4]
MOVS R1,#+4096
CMP R0,R1
BEQ.N ??USART_Init_3
MOVS R1,#+136
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_3:
LDRH R0,[R6, #+6]
CMP R0,#+0
BEQ.N ??USART_Init_4
LDRH R0,[R6, #+6]
MOVS R1,#+4096
CMP R0,R1
BEQ.N ??USART_Init_4
LDRH R0,[R6, #+6]
MOVS R1,#+8192
CMP R0,R1
BEQ.N ??USART_Init_4
LDRH R0,[R6, #+6]
MOVS R1,#+12288
CMP R0,R1
BEQ.N ??USART_Init_4
MOVS R1,#+137
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_4:
LDRH R0,[R6, #+8]
CMP R0,#+0
BEQ.N ??USART_Init_5
LDRH R0,[R6, #+8]
MOVS R1,#+1024
CMP R0,R1
BEQ.N ??USART_Init_5
LDRH R0,[R6, #+8]
MOVS R1,#+1536
CMP R0,R1
BEQ.N ??USART_Init_5
MOVS R1,#+138
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_5:
LDRH R0,[R6, #+10]
CMP R0,#+0
BEQ.N ??USART_Init_6
LDRH R0,[R6, #+10]
MOVS R1,#+256
CMP R0,R1
BEQ.N ??USART_Init_6
LDRH R0,[R6, #+10]
MOVS R1,#+512
CMP R0,R1
BEQ.N ??USART_Init_6
LDRH R0,[R6, #+10]
MOVS R1,#+768
CMP R0,R1
BEQ.N ??USART_Init_6
MOVS R1,#+139
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_6:
LDRH R0,[R6, #+12]
LDR.N R1,??USART_Init_1+0x4 ;; 0xfff3
TST R0,R1
BNE.N ??USART_Init_7
LDRH R0,[R6, #+12]
CMP R0,#+0
BNE.N ??USART_Init_8
??USART_Init_7:
MOVS R1,#+140
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_8:
LDRH R0,[R6, #+14]
CMP R0,#+0
BEQ.N ??USART_Init_9
LDRH R0,[R6, #+14]
MOVS R1,#+2048
CMP R0,R1
BEQ.N ??USART_Init_9
MOVS R1,#+141
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_9:
LDRH R0,[R6, #+16]
CMP R0,#+0
BEQ.N ??USART_Init_10
LDRH R0,[R6, #+16]
MOVS R1,#+1024
CMP R0,R1
BEQ.N ??USART_Init_10
MOVS R1,#+142
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_10:
LDRH R0,[R6, #+18]
CMP R0,#+0
BEQ.N ??USART_Init_11
LDRH R0,[R6, #+18]
MOVS R1,#+512
CMP R0,R1
BEQ.N ??USART_Init_11
MOVS R1,#+143
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_11:
LDRH R0,[R6, #+20]
CMP R0,#+0
BEQ.N ??USART_Init_12
LDRH R0,[R6, #+20]
MOVS R1,#+256
CMP R0,R1
BEQ.N ??USART_Init_12
MOVS R1,#+144
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
_BLF assert_failed,??assert_failed??rT
??USART_Init_12:
LDRH R5,[R4, #+16]
MOVS R0,R5
LDR.N R5,??USART_Init_1+0x8 ;; 0xc0ff
ANDS R5,R5,R0
LDRH R0,[R6, #+6]
LDRH R1,[R6, #+14]
ORRS R1,R1,R0
LDRH R0,[R6, #+16]
ORRS R0,R0,R1
LDRH R1,[R6, #+18]
ORRS R1,R1,R0
LDRH R0,[R6, #+20]
ORRS R0,R0,R1
ORRS R0,R0,R5
MOVS R5,R0
STRH R5,[R4, #+16]
MOVS R5,#+0
LDRH R0,[R4, #+12]
MOVS R5,R0
MOVS R0,R5
LDR.N R5,??USART_Init_1+0xC ;; 0xe9f3
ANDS R5,R5,R0
LDRH R0,[R6, #+4]
LDRH R1,[R6, #+8]
ORRS R1,R1,R0
LDRH R0,[R6, #+12]
ORRS R0,R0,R1
ORRS R0,R0,R5
MOVS R5,R0
STRH R5,[R4, #+12]
MOVS R5,#+0
LDRH R0,[R4, #+20]
MOVS R5,R0
MOVS R0,R5
LDR.N R5,??USART_Init_1+0x10 ;; 0xfcff
ANDS R5,R5,R0
MOVS R0,R5
LDRH R5,[R6, #+10]
ORRS R5,R5,R0
STRH R5,[R4, #+20]
MOVS R5,#+0
MOV R0,SP
_BLF RCC_GetClocksFreq,??RCC_GetClocksFreq??rT
LDR.N R0,??DataTable11 ;; 0x40013800
CMP R4,R0
BNE.N ??USART_Init_13
LDR R0,[SP, #+12]
B.N ??USART_Init_14
??USART_Init_13:
LDR R0,[SP, #+8]
??USART_Init_14:
MOVS R1,#+25
MULS R0,R1,R0
LDR R1,[R6, #+0]
MOVS R2,#+4
MULS R1,R2,R1
UDIV R1,R0,R1
MOVS R0,#+100
UDIV R0,R1,R0
LSLS R5,R0,#+4
MOVS R0,R5
LSRS R0,R0,#+4
MOVS R2,#+100
MLS R2,R0,R2,R1
MOVS R0,#+16
MULS R2,R0,R2
ADDS R2,R2,#+50
MOVS R0,#+100
UDIV R0,R2,R0
LSLS R0,R0,#+28 ;; ZeroExtS R0,R0,#+28,#+28
LSRS R0,R0,#+28
ORRS R0,R0,R5
MOVS R5,R0
STRH R5,[R4, #+8]
ADD SP,SP,#+20
POP {R4-R6,PC} ;; return
DATA
??USART_Init_1:
DC32 0x44aa21
DC32 0xfff3
DC32 0xc0ff
DC32 0xe9f3
DC32 0xfcff
RSEG CODE:CODE:NOROOT(2)
DATA
??DataTable11:
DC32 0x40013800
RSEG CODE:CODE:NOROOT(2)
THUMB
USART_StructInit:
MOVS R1,#+9600
STR R1,[R0, #+0]
MOVS R1,#+0
STRH R1,[R0, #+4]
MOVS R1,#+0
STRH R1,[R0, #+6]
MOVS R1,#+0
STRH R1,[R0, #+8]
MOVS R1,#+0
STRH R1,[R0, #+10]
MOVS R1,#+12
STRH R1,[R0, #+12]
MOVS R1,#+0
STRH R1,[R0, #+14]
MOVS R1,#+0
STRH R1,[R0, #+16]
MOVS R1,#+0
STRH R1,[R0, #+18]
MOVS R1,#+0
STRH R1,[R0, #+20]
BX LR ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
USART_Cmd:
PUSH {R4,R5,LR}
MOVS R4,R0
MOVS R5,R1
CMP R5,#+0
BEQ.N ??USART_Cmd_0
CMP R5,#+1
BEQ.N ??USART_Cmd_0
MOVS R1,#+254
LDR.N R0,??DataTable22 ;; `?<Constant "C:\\\\David JIANG\\\\ST MCU...">`
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