?? stm32f10x_tim1.s79
字號:
//////////////////////////////////////////////////////////////////////////////
// /
// IAR ARM ANSI C/C++ Compiler V4.42A/W32 15/May/2008 12:06:34 /
// Copyright 1999-2005 IAR Systems. All rights reserved. /
// /
// Cpu mode = thumb /
// Endian = little /
// Stack alignment = 4 /
// Source file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_tim1.c /
// Command line = "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\FWLib\src\stm32f10x_tim1.c" -D /
// VECT_TAB_FLASH -lcN "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" /
// -lb "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\" -o /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\Obj\" -z3 /
// --no_cse --no_unroll --no_inline --no_code_motion /
// --no_tbaa --no_clustering --no_scheduling --debug /
// --cpu_mode thumb --endian little --cpu cortex-M3 /
// --stack_align 4 --require_prototypes --fpu None /
// --dlib_config "C:\Program Files\IAR /
// Systems\Embedded Workbench /
// 4.0\arm\LIB\dl7mptnnl8f.h" -I "C:\David JIANG\ST /
// MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\" -I "C:\David /
// JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\include\" -I /
// "C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\..\..\FWLib\inc\" -I /
// "C:\Program Files\IAR Systems\Embedded Workbench /
// 4.0\arm\INC\" /
// List file = C:\David JIANG\ST MCU\Docs\STM32\AN_JIANG\TIM /
// Encoder\example\project\EWARM\BOOT_FLASH\List\stm32 /
// f10x_tim1.s79 /
// /
// /
//////////////////////////////////////////////////////////////////////////////
NAME stm32f10x_tim1
RSEG CSTACK:DATA:NOROOT(2)
??DataTable0 EQU 0
??DataTable1 EQU 0
??DataTable10 EQU 0
??DataTable100 EQU 0
??DataTable101 EQU 0
??DataTable102 EQU 0
??DataTable103 EQU 0
??DataTable105 EQU 0
??DataTable106 EQU 0
??DataTable107 EQU 0
??DataTable108 EQU 0
??DataTable109 EQU 0
??DataTable11 EQU 0
??DataTable110 EQU 0
??DataTable111 EQU 0
??DataTable112 EQU 0
??DataTable113 EQU 0
??DataTable114 EQU 0
??DataTable117 EQU 0
??DataTable118 EQU 0
??DataTable119 EQU 0
??DataTable12 EQU 0
??DataTable120 EQU 0
??DataTable121 EQU 0
??DataTable122 EQU 0
??DataTable123 EQU 0
??DataTable124 EQU 0
??DataTable125 EQU 0
??DataTable127 EQU 0
??DataTable128 EQU 0
??DataTable129 EQU 0
??DataTable13 EQU 0
??DataTable130 EQU 0
??DataTable131 EQU 0
??DataTable132 EQU 0
??DataTable133 EQU 0
??DataTable134 EQU 0
??DataTable135 EQU 0
??DataTable136 EQU 0
??DataTable137 EQU 0
??DataTable138 EQU 0
??DataTable139 EQU 0
??DataTable14 EQU 0
??DataTable140 EQU 0
??DataTable141 EQU 0
??DataTable142 EQU 0
??DataTable143 EQU 0
??DataTable144 EQU 0
??DataTable148 EQU 0
??DataTable149 EQU 0
??DataTable15 EQU 0
??DataTable152 EQU 0
??DataTable153 EQU 0
??DataTable154 EQU 0
??DataTable155 EQU 0
??DataTable156 EQU 0
??DataTable157 EQU 0
??DataTable158 EQU 0
??DataTable159 EQU 0
??DataTable16 EQU 0
??DataTable160 EQU 0
??DataTable161 EQU 0
??DataTable162 EQU 0
??DataTable163 EQU 0
??DataTable164 EQU 0
??DataTable166 EQU 0
??DataTable167 EQU 0
??DataTable168 EQU 0
??DataTable17 EQU 0
??DataTable171 EQU 0
??DataTable172 EQU 0
??DataTable173 EQU 0
??DataTable174 EQU 0
??DataTable175 EQU 0
??DataTable176 EQU 0
??DataTable177 EQU 0
??DataTable178 EQU 0
??DataTable179 EQU 0
??DataTable18 EQU 0
??DataTable180 EQU 0
??DataTable181 EQU 0
??DataTable182 EQU 0
??DataTable184 EQU 0
??DataTable185 EQU 0
??DataTable186 EQU 0
??DataTable187 EQU 0
??DataTable188 EQU 0
??DataTable189 EQU 0
??DataTable190 EQU 0
??DataTable192 EQU 0
??DataTable194 EQU 0
??DataTable196 EQU 0
??DataTable198 EQU 0
??DataTable2 EQU 0
??DataTable200 EQU 0
??DataTable202 EQU 0
??DataTable204 EQU 0
??DataTable205 EQU 0
??DataTable206 EQU 0
??DataTable207 EQU 0
??DataTable208 EQU 0
??DataTable209 EQU 0
??DataTable210 EQU 0
??DataTable215 EQU 0
??DataTable216 EQU 0
??DataTable218 EQU 0
??DataTable219 EQU 0
??DataTable220 EQU 0
??DataTable221 EQU 0
??DataTable223 EQU 0
??DataTable224 EQU 0
??DataTable225 EQU 0
??DataTable226 EQU 0
??DataTable228 EQU 0
??DataTable229 EQU 0
??DataTable23 EQU 0
??DataTable230 EQU 0
??DataTable231 EQU 0
??DataTable233 EQU 0
??DataTable234 EQU 0
??DataTable235 EQU 0
??DataTable237 EQU 0
??DataTable238 EQU 0
??DataTable239 EQU 0
??DataTable24 EQU 0
??DataTable240 EQU 0
??DataTable241 EQU 0
??DataTable242 EQU 0
??DataTable243 EQU 0
??DataTable244 EQU 0
??DataTable245 EQU 0
??DataTable246 EQU 0
??DataTable247 EQU 0
??DataTable248 EQU 0
??DataTable249 EQU 0
??DataTable25 EQU 0
??DataTable250 EQU 0
??DataTable251 EQU 0
??DataTable252 EQU 0
??DataTable254 EQU 0
??DataTable255 EQU 0
??DataTable256 EQU 0
??DataTable258 EQU 0
??DataTable26 EQU 0
??DataTable260 EQU 0
??DataTable261 EQU 0
??DataTable262 EQU 0
??DataTable263 EQU 0
??DataTable264 EQU 0
??DataTable265 EQU 0
??DataTable266 EQU 0
??DataTable267 EQU 0
??DataTable268 EQU 0
??DataTable269 EQU 0
??DataTable27 EQU 0
??DataTable270 EQU 0
??DataTable271 EQU 0
??DataTable272 EQU 0
??DataTable273 EQU 0
??DataTable274 EQU 0
??DataTable275 EQU 0
??DataTable277 EQU 0
??DataTable279 EQU 0
??DataTable28 EQU 0
??DataTable280 EQU 0
??DataTable281 EQU 0
??DataTable282 EQU 0
??DataTable285 EQU 0
??DataTable286 EQU 0
??DataTable287 EQU 0
??DataTable288 EQU 0
??DataTable29 EQU 0
??DataTable291 EQU 0
??DataTable292 EQU 0
??DataTable294 EQU 0
??DataTable297 EQU 0
??DataTable298 EQU 0
??DataTable3 EQU 0
??DataTable31 EQU 0
??DataTable32 EQU 0
??DataTable33 EQU 0
??DataTable39 EQU 0
??DataTable4 EQU 0
??DataTable40 EQU 0
??DataTable41 EQU 0
??DataTable42 EQU 0
??DataTable43 EQU 0
??DataTable44 EQU 0
??DataTable45 EQU 0
??DataTable46 EQU 0
??DataTable47 EQU 0
??DataTable48 EQU 0
??DataTable5 EQU 0
??DataTable53 EQU 0
??DataTable54 EQU 0
??DataTable55 EQU 0
??DataTable56 EQU 0
??DataTable57 EQU 0
??DataTable58 EQU 0
??DataTable59 EQU 0
??DataTable6 EQU 0
??DataTable60 EQU 0
??DataTable63 EQU 0
??DataTable64 EQU 0
??DataTable65 EQU 0
??DataTable66 EQU 0
??DataTable67 EQU 0
??DataTable68 EQU 0
??DataTable7 EQU 0
??DataTable70 EQU 0
??DataTable72 EQU 0
??DataTable73 EQU 0
??DataTable74 EQU 0
??DataTable75 EQU 0
??DataTable76 EQU 0
??DataTable77 EQU 0
??DataTable78 EQU 0
??DataTable79 EQU 0
??DataTable8 EQU 0
??DataTable80 EQU 0
??DataTable81 EQU 0
??DataTable82 EQU 0
??DataTable83 EQU 0
??DataTable85 EQU 0
??DataTable86 EQU 0
??DataTable87 EQU 0
??DataTable88 EQU 0
??DataTable89 EQU 0
??DataTable9 EQU 0
??DataTable90 EQU 0
??DataTable91 EQU 0
??DataTable92 EQU 0
??DataTable93 EQU 0
??DataTable94 EQU 0
??DataTable95 EQU 0
??DataTable96 EQU 0
??DataTable97 EQU 0
??DataTable98 EQU 0
??DataTable99 EQU 0
MULTWEAK ??RCC_APB2PeriphResetCmd??rT
MULTWEAK ??assert_failed??rT
PUBLIC TIM1_ARRPreloadConfig
PUBLIC TIM1_BDTRConfig
PUBLIC TIM1_BDTRStructInit
PUBLIC TIM1_CCPreloadControl
PUBLIC TIM1_CCxCmd
PUBLIC TIM1_CCxNCmd
PUBLIC TIM1_ClearFlag
PUBLIC TIM1_ClearITPendingBit
PUBLIC TIM1_ClearOC1Ref
PUBLIC TIM1_ClearOC2Ref
PUBLIC TIM1_ClearOC3Ref
PUBLIC TIM1_ClearOC4Ref
PUBLIC TIM1_Cmd
PUBLIC TIM1_CounterModeConfig
PUBLIC TIM1_CtrlPWMOutputs
PUBLIC TIM1_DMACmd
PUBLIC TIM1_DMAConfig
PUBLIC TIM1_DeInit
PUBLIC TIM1_ETRClockMode1Config
PUBLIC TIM1_ETRClockMode2Config
PUBLIC TIM1_ETRConfig
PUBLIC TIM1_EncoderInterfaceConfig
PUBLIC TIM1_ForcedOC1Config
PUBLIC TIM1_ForcedOC2Config
PUBLIC TIM1_ForcedOC3Config
PUBLIC TIM1_ForcedOC4Config
PUBLIC TIM1_GenerateEvent
PUBLIC TIM1_GetCapture1
PUBLIC TIM1_GetCapture2
PUBLIC TIM1_GetCapture3
PUBLIC TIM1_GetCapture4
PUBLIC TIM1_GetCounter
PUBLIC TIM1_GetFlagStatus
PUBLIC TIM1_GetITStatus
PUBLIC TIM1_GetPrescaler
PUBLIC TIM1_ICInit
PUBLIC TIM1_ICStructInit
PUBLIC TIM1_ITConfig
PUBLIC TIM1_ITRxExternalClockConfig
PUBLIC TIM1_InternalClockConfig
PUBLIC TIM1_OC1FastConfig
PUBLIC TIM1_OC1Init
PUBLIC TIM1_OC1NPolarityConfig
PUBLIC TIM1_OC1PolarityConfig
PUBLIC TIM1_OC1PreloadConfig
PUBLIC TIM1_OC2FastConfig
PUBLIC TIM1_OC2Init
PUBLIC TIM1_OC2NPolarityConfig
PUBLIC TIM1_OC2PolarityConfig
PUBLIC TIM1_OC2PreloadConfig
PUBLIC TIM1_OC3FastConfig
PUBLIC TIM1_OC3Init
PUBLIC TIM1_OC3NPolarityConfig
PUBLIC TIM1_OC3PolarityConfig
PUBLIC TIM1_OC3PreloadConfig
PUBLIC TIM1_OC4FastConfig
PUBLIC TIM1_OC4Init
PUBLIC TIM1_OC4PolarityConfig
PUBLIC TIM1_OC4PreloadConfig
PUBLIC TIM1_OCStructInit
PUBLIC TIM1_PWMIConfig
PUBLIC TIM1_PrescalerConfig
PUBLIC TIM1_SelectCCDMA
PUBLIC TIM1_SelectCOM
PUBLIC TIM1_SelectHallSensor
PUBLIC TIM1_SelectInputTrigger
PUBLIC TIM1_SelectMasterSlaveMode
PUBLIC TIM1_SelectOCxM
PUBLIC TIM1_SelectOnePulseMode
PUBLIC TIM1_SelectOutputTrigger
PUBLIC TIM1_SelectSlaveMode
PUBLIC TIM1_SetAutoreload
PUBLIC TIM1_SetClockDivision
PUBLIC TIM1_SetCompare1
PUBLIC TIM1_SetCompare2
PUBLIC TIM1_SetCompare3
PUBLIC TIM1_SetCompare4
PUBLIC TIM1_SetCounter
PUBLIC TIM1_SetIC1Prescaler
PUBLIC TIM1_SetIC2Prescaler
PUBLIC TIM1_SetIC3Prescaler
PUBLIC TIM1_SetIC4Prescaler
PUBLIC TIM1_TIxExternalClockConfig
PUBLIC TIM1_TimeBaseInit
PUBLIC TIM1_TimeBaseStructInit
PUBLIC TIM1_UpdateDisableConfig
PUBLIC TIM1_UpdateRequestConfig
RCC_APB2PeriphResetCmd SYMBOL "RCC_APB2PeriphResetCmd"
assert_failed SYMBOL "assert_failed"
??RCC_APB2PeriphResetCmd??rT SYMBOL "??rT", RCC_APB2PeriphResetCmd
??assert_failed??rT SYMBOL "??rT", assert_failed
EXTERN RCC_APB2PeriphResetCmd
EXTERN TIM1
EXTERN assert_failed
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_DeInit:
PUSH {LR}
MOVS R1,#+1
MOVS R0,#+2048
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
MOVS R1,#+0
MOVS R0,#+2048
_BLF RCC_APB2PeriphResetCmd,??RCC_APB2PeriphResetCmd??rT
POP {PC} ;; return
RSEG CODE:CODE:NOROOT(2)
THUMB
TIM1_TimeBaseInit:
PUSH {R4,LR}
MOVS R4,R0
LDRH R0,[R4, #+2]
CMP R0,#+0
BEQ.N ??TIM1_TimeBaseInit_0
LDRH R0,[R4, #+2]
CMP R0,#+16
BEQ.N ??TIM1_TimeBaseInit_0
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -