MEMORY
{
	PAGE 0:
		VECS : o= 0000h, l=40h  
		PVECS: o=44h,	 l=100h/*peripheral interrupt vectors*/
		PROG:  o=200h,	 l=0fe00h/*afh0-7fffh,flash*/
		/*SRAM : o= 0700h,l=0c0h */
	PAGE 1:
		MMRS:  o=0h,l=60h
		B2  :  o=0060h,l=20h
		B01 :  o=0200h,l=80h
		B02 :  o=0280h,l=80h
		B11 :  o=0300h,l=80h
		B12 :  o=0380h,l=80h
		SARAM1:o=0800h,l=80h  
		SARAM2:o=0880h,l=80h
		SARAM3:o=0900h,l=100h
		SARAM5:o=0a00h,l=200h
		SARAM7:o=0c00h,l=80h
		SARAM9:o=0d00h,l=300h
		DRAM : o=8000h,l=8000h 	
}
SECTIONS
{
	.reset	: {}> VECS PAGE 0/*Interrupt Vector Table*/ 
	.vectors: {}> VECS PAGE 0
	.pvecs	: {}> PVECS PAGE 0
	.text   : {}> PROG PAGE 0  /*CODE*/
	.const1	: {}> PROG PAGE 0
	/*.const	: LOAD=PROG PAGE 0,RUN=B01 PAGE 1*/  
	.init	: {}> PROG	PAGE 0    /*FFT*/
	.cinit	: {}> PROG 	PAGE 0
	.b2		: {}> B2	PAGE 1
	.contex : {}> B01	PAGE 1
	.stack  : {}> B01	PAGE 1
	.data0  : {}> B02	PAGE 1
	.data1  : {}> B11	PAGE 1
	.user	: {}> SARAM1 PAGE 1   
	.user1	: {}> SARAM2 PAGE 1
	.user2	: {}> SARAM3 PAGE 1  
	.user3	: {}> SARAM5 PAGE 1
}