?? 2407.h
字號:
;*************************************************************
; File Name: 240x.h
;
; Description: 240x Peripheral Registers + other useful definitions
;
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000 Release Rev 1.0
;=====================================================================================
;--------------------------------------------------------------
; On Chip Periperal Register Definitions
;--------------------------------------------------------------
;C2xx Core Registers
;**************************
PIVR .set 0701EH ;系統中斷矢量寄存器
;~~~~~~~~~~~~~~~~~~~~
IMR .set 0004h ; Int Mask
GREG .set 0005h ; Global memory allocation
IFR .set 0006h ; Int Flag
ABRPT .set 01fh ; Analysis BreakPoint
WSGR .set 0FFFFh ; Wait State Control (IO space mapped)
FCMR .set 0FF0Fh ; Flash control mode register
;System Module Registers
;~~~~~~~~~~~~~~~~~~~~~~~
SCSR1 .set 7018h ; System contr & stat 1 (240x only)
SCSR2 .set 7019h ; System contr & stat 2 (240x only)
DINR .set 701Ch ; Device Identification Register
PIRQR0 .set 7010h ; Peripheral Interrupt Request Reg0(241/2/3,240x only)
PIRQR1 .set 7011h ; Peripheral Interrupt Request Reg1(241/2/3,240x only)
PIRQR2 .set 7012h ; Peripheral Interrupt Request Reg2(240x only)
PIACKR0 .set 7014h ; Peripheral Interrupt Acknowledge Reg0(241/2/3,240x only)
PIACKR1 .set 7015h ; Peripheral Interrupt Acknowledge Reg1(241/2/3,240x only)
PIACKR2 .set 7016h ; Peripheral Interrupt Acknowledge Reg2(240x only)
; External interrupt configuration registers
XINT1CR .set 7070h ; Int1 config. X241/2/3, (X240x only)
XINT2CR .set 7071h ; Int2 config. X241/2/3, (X240x only)
;Digital I/O
;~~~~~~~~~~~
MCRA .set 7090h ;I/O Mux Control Reg A
MCRB .set 7092h ;I/O Mux Control Reg B
MCRC .set 7094h ;I/O Mux Control Reg C
PADATDIR .set 7098h ;I/O port A Data & Direction
PBDATDIR .set 709Ah ;I/O port B Data & Direction
PCDATDIR .set 709Ch ;I/O port C Data & Direction
PDDATDIR .set 709Eh ;I/O port D Data & Direction
PEDATDIR .set 7095h ;I/O port E Data & Direction
PFDATDIR .set 7096h ;I/O port F Data & Direction
;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
RTI_CNTR .set 7021h ; RTI Counter reg
WD_CNTR .set 7023h ; WD Counter reg
WD_KEY .set 7025h ; WD Key reg
WDKEY .set WD_KEY
RTI_CNTL .set 7027h ; RTI Control reg
WD_CNTL .set 7029h ; WD Control reg
WDCR .set WD_CNTL
PLL_CNTL1 .set 702Bh ; PLL control reg 1
PLL_CNTL2 .set 702Dh ; PLL control reg 2
;--------------------------------------------------------------
; ADC Register declarations - x240x
;--------------------------------------------------------------
;ADCL_CNTL1 .set 70A0h ;ADC Control reg 1
;ADCL_CNTL2 .set 70A1h ;ADC Control reg 2
ADCTRL1 .set 70A0h ;ADC Control reg 1
ADCTRL2 .set 70A1h ;ADC Control reg 2
MAXCONV .set 70A2h ;Maximum conversions in sequence
CHSELSEQ1 .set 70A3h ;Channel select fields: Results 3,2,1,0
CHSELSEQ2 .set 70A4h ;Channel select fields: Results 7,6,5,4
CHSELSEQ3 .set 70A5h ;Channel select fields: Results 11,10,9,8
CHSELSEQ4 .set 70A6h ;Channel select fields: Results 15,14,13,12
AUTO_SEQ_SR .set 70A7h ;Auto-sequence status Register
ADC_RESULT0 .set 70A8h ;Conversion result 0
ADC_RESULT1 .set 70A9h ;Conversion result 1
ADC_RESULT2 .set 70AAh ;Conversion result 2
ADC_RESULT3 .set 70ABh ;Conversion result 3
ADC_RESULT4 .set 70ACh ;Conversion result 4
ADC_RESULT5 .set 70ADh ;Conversion result 5
ADC_RESULT6 .set 70AEh ;Conversion result 6
ADC_RESULT7 .set 70AFh ;Conversion result 7
ADC_RESULT8 .set 70B0h ;Conversion result 8
ADC_RESULT9 .set 70B1h ;Conversion result 9
ADC_RESULT10 .set 70B2h ;Conversion result 10
ADC_RESULT11 .set 70B3h ;Conversion result 11
ADC_RESULT12 .set 70B4h ;Conversion result 12
ADC_RESULT13 .set 70B5h ;Conversion result 13
ADC_RESULT14 .set 70B6h ;Conversion result 14
ADC_RESULT15 .set 70B7h ;Conversion result 15
CALIBRATION .set 70B8h ;Calibration Register
;Serial Peripheral Interface (SPI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPICCR .set 7040h ;SPI Config Control Reg 1
SPICTL .set 7041h ;SPI Operation Control Reg 2
SPISTS .set 7042h ;SPI Status Reg
SPIBRR .set 7044h ;SPI Baud rate control reg
SPIRXEMU .set 7046h ;SPI Emulation buffer reg
SPIRXBUF .set 7047h ;SPI Serial Input buffer reg
SPITXBUF .set 7048h ;SPI Serial Output buffer reg
SPIDAT .set 7049h ;SPI Serial Data reg
SPIPRI .set 704Fh ;SPI Priority control reg
;Serial Communications Interface (SCI) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SCICCR .set 7050h ;SCI Comms Control Reg
SCICTL1 .set 7051h ;SCI Control Reg 1
SCIHBAUD .set 7052h ;SCI Baud rate control
SCILBAUD .set 7053h ;SCI Baud rate control
SCICTL2 .set 7054h ;SCI Control Reg 2
SCIRXST .set 7055h ;SCI Receive status reg
SCIRXEMU .set 7056h ;SCI EMU data buffer
SCIRXBUF .set 7057h ;SCI Receive data buffer
SCITXBUF .set 7059h ;SCI Transmit data buffer
SCIPRI .set 705Fh ;SCI Priority control reg
;Event Manager (EV)/Event Manager A (EVA) Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONA .set 7400h ; General Timer Control
T1CNT .set 7401h ; T1 Counter
T1CMPR .set 7402h ; T1 Compare Value
T1PR .set 7403h ; T1 Period
T1CON .set 7404h ; T1 Control
T2CNT .set 7405h ; T2 Counter
T2CMPR .set 7406h ; T2 Compare Value
T2PR .set 7407h ; T2 Period
T2CON .set 7408h ; T2 Control
COMCONA .set 7411h ; Compare Control
ACTRA .set 7413h ; Compare Output Action Control
DBTCONA .set 7415h ; Dead Band Control
CMPR1 .set 7417h ; Compare Value 1
CMPR2 .set 7418h ; Compare Value 2
CMPR3 .set 7419h ; Compare Value 3
CAPCONA .set 7420h ; Capture Control
CAPFIFOA .set 7422h ; Capture FIFO1-3/4 Status
CAP1FIFO .set 7423h ; Capture 1 FIFO Top
CAP2FIFO .set 7424h ; Capture 2 FIFO Top
CAP3FIFO .set 7425h ; Capture 3 FIFO Top
CAP1FBOT .set 7427h ; Capture 1 FIFO Bottom
CAP2FBOT .set 7428h ; Capture 2 FIFO Bottom
CAP3FBOT .set 7429h ; Capture 3 FIFO Bottom
EVAIMRA .set 742Ch ; Group A Int Mask
EVAIMRB .set 742Dh ; Group B Int Mask
EVAIMRC .set 742Eh ; Group C Int Mask
EVAIFRA .set 742Fh ; Group A Int Flag
EVAIFRB .set 7430h ; Group B Int Flag
EVAIFRC .set 7431h ; Group C Int Flag
;Event Manager B (EVB) Registers (240x Only)
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
GPTCONB .set 7500h ; General Timer Control
T3CNT .set 7501h ; T1 Counter
T3CMPR .set 7502h ; T1 Comp Value
T3PR .set 7503h ; T1 Period
T3CON .set 7504h ; T1 Control
T4CNT .set 7505h ; T2 Counter
T4CMPR .set 7506h ; T2 Comp Value
T4PR .set 7507h ; T2 Period
T4CON .set 7508h ; T2 Control
COMCONB .set 7511h ; Compare Control
ACTRB .set 7513h ; Compare Output Action Control
DBTCONB .set 7515h ; Dead Band Control
CMPR4 .set 7517h ; Comp Value 4
CMPR5 .set 7518h ; Comp Value 5
CMPR6 .set 7519h ; Comp Value 6
CAPCONB .set 7520h ; Capture Control
CAPFIFOB .set 7522h ; Capture FIFO4-6 Status
CAP4FIFO .set 7523h ; Capture 4 FIFO Top
CAP5FIFO .set 7524h ; Capture 5 FIFO Top
CAP6FIFO .set 7525h ; Capture 6 FIFO Top
CAP4FBOT .set 7527h ; Capture 4 FIFO Bottom
CAP5FBOT .set 7528h ; Capture 5 FIFO Bottom
CAP6FBOT .set 7529h ; Capture 6 FIFO Bottom
I
EVBIMRA .set 752ch ; Group A Int Mask
EVBIMRB .set 752dh ; Group B Int Mask
EVBIMRC .set 752eh ; Group C Int Mask
EVBIFRA .set 752fh ; Group A Int Flag
EVBIFRB .set 7530h ; Group B Int Flag
EVBIFRC .set 7531h ; Group C Int Flag
;-----------------------------------------------------------------------------
; CAN register
;-----------------------------------------------------------------------------
MDER .set 7100h ; CAN Mailbox Direction/Enable register
TCR .set 7101h ; CAN Transmission Control register
RCR .set 7102h ; CAN Recieve Control register
MCR .set 7103h ; CAN Master Control register
BCR2 .set 7104h ; CAN Bit Config register 2
BCR1 .set 7105h ; CAN Bit Config register 1
ESR .set 7106h ; CAN Error Status register
GSR .set 7107h ; CAN Global Status register
CEC .set 7108h ; CAN Trans and Rcv Err counters
CAN_IFR .set 7109h ; CAN Interrupt Flag Register
CAN_IMR .set 710ah ; CAN Interrupt Mask Register
LAM0H .set 710bh ; CAN Local Acceptance Mask MBX0/1
LAM0L .set 710ch ; CAN Local Acceptance Mask MBX0/1
LAM1H .set 710dh ; CAN Local Acceptance Mask MBX2/3
LAM1L .set 710eh ; CAN Local Acceptance Mask MBX2/3
MSGID0L .set 7200h ; CAN Message ID for mailbox 0 (lower 16 bits)
MSGID0H .set 7201h ; CAN Message ID for mailbox 0 (upper 16 bits)
MSGCTRL0 .set 7202h ; CAN RTR and DLC
MBX0A .set 7204h ; CAN 2 of 8 bytes of Mailbox 0
MBX0B .set 7205h ; CAN 2 of 8 bytes of Mailbox 0
MBX0C .set 7206h ; CAN 2 of 8 bytes of Mailbox 0
MBX0D .set 7207h ; CAN 2 of 8 bytes of Mailbox 0
MSGID1L .set 7208h ; CAN Message ID for mailbox 1 (lower 16 bits)
MSGID1H .set 7209h ; CAN Message ID for mailbox 1 (upper 16 bits)
MSGCTRL1 .set 720Ah ; CAN RTR and DLC
MBX1A .set 720Ch ; CAN 2 of 8 bytes of Mailbox 1
MBX1B .set 720Dh ; CAN 2 of 8 bytes of Mailbox 1
MBX1C .set 720Eh ; CAN 2 of 8 bytes of Mailbox 1
MBX1D .set 720Fh ; CAN 2 of 8 bytes of Mailbox 1
MSGID2L .set 7210h ; CAN Message ID for mailbox 2 (lower 16 bits)
MSGID2H .set 7211h ; CAN Message ID for mailbox 2 (upper 16 bits)
MSGCTRL2 .set 7212h ; CAN RTR and DLC
MBX2A .set 7214h ; CAN 2 of 8 bytes of Mailbox 2
MBX2B .set 7215h ; CAN 2 of 8 bytes of Mailbox 2
MBX2C .set 7216h ; CAN 2 of 8 bytes of Mailbox 2
MBX2D .set 7217h ; CAN 2 of 8 bytes of Mailbox 2
MSGID3L .set 7218h ; CAN Message ID for mailbox 3 (lower 16 bits)
MSGID3H .set 7219h ; CAN Message ID for mailbox 3 (upper 16 bits)
MSGCTRL3 .set 721Ah ; CAN RTR and DLC
MBX3A .set 721Ch ; CAN 2 of 8 bytes of Mailbox 3
MBX3B .set 721Dh ; CAN 2 of 8 bytes of Mailbox 3
MBX3C .set 721Eh ; CAN 2 of 8 bytes of Mailbox 3
MBX3D .set 721Fh ; CAN 2 of 8 bytes of Mailbox 3
MSGID4L .set 7220h ; CAN Message ID for mailbox 4 (lower 16 bits)
MSGID4H .set 7221h ; CAN Message ID for mailbox 4 (upper 16 bits)
MSGCTRL4 .set 7222h ; CAN RTR and DLC
MBX4A .set 7224h ; CAN 2 of 8 bytes of Mailbox 4
MBX4B .set 7225h ; CAN 2 of 8 bytes of Mailbox 4
MBX4C .set 7226h ; CAN 2 of 8 bytes of Mailbox 4
MBX4D .set 7227h ; CAN 2 of 8 bytes of Mailbox 4
MSGID5L .set 7228h ; CAN Message ID for mailbox 5 (lower 16 bits)
MSGID5H .set 7229h ; CAN Message ID for mailbox 5 (upper 16 bits)
MSGCTRL5 .set 722Ah ; CAN RTR and DLC
MBX5A .set 722Ch ; CAN 2 of 8 bytes of Mailbox 5
MBX5B .set 722Dh ; CAN 2 of 8 bytes of Mailbox 5
MBX5C .set 722Eh ; CAN 2 of 8 bytes of Mailbox 5
MBX5D .set 722Fh ; CAN 2 of 8 bytes of Mailbox 5
;-----------------------------------------------------------------------------
; Bit codes for Test bit instruction (BIT)
;-----------------------------------------------------------------------------
BIT15 .set 0000h ;Bit Code for 15
BIT14 .set 0001h ;Bit Code for 14
BIT13 .set 0002h ;Bit Code for 13
BIT12 .set 0003h ;Bit Code for 12
BIT11 .set 0004h ;Bit Code for 11
BIT10 .set 0005h ;Bit Code for 10
BIT9 .set 0006h ;Bit Code for 9
BIT8 .set 0007h ;Bit Code for 8
BIT7 .set 0008h ;Bit Code for 7
BIT6 .set 0009h ;Bit Code for 6
BIT5 .set 000Ah ;Bit Code for 5
BIT4 .set 000Bh ;Bit Code for 4
BIT3 .set 000Ch ;Bit Code for 3
BIT2 .set 000Dh ;Bit Code for 2
BIT1 .set 000Eh ;Bit Code for 1
BIT0 .set 000Fh ;Bit Code for 0
;External Data Space Registers
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
EXTDATA .set 8000h
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
;經常使用的數據頁
DP_USER .set 5
DP_B2 .set 0 ;頁 0 數據空間
DP_B01 .set 4 ;頁 4 B0(200H/80H)
DP_B02 .set 5 ;頁 5 B0(280H/80H)
DP_B11 .set 6 ;頁 6 B1(300H/80H)
DP_B12 .set 7 ;頁 7 AD(380H/80H)
DP_SARAM1 .set 16 ;頁 1 SARAM(800h/80h)
DP_SARAM2 .set 26 ;頁 2 SARAM(0D00h/80h)
DP_SARAM3 .set 18 ;頁 3 SARAM(900h/80h)
DP_SARAM4 .set 19 ;頁 4 SARAM(980h/80h)
DP_PF1 .set 224 ;頁 1 外設幀文件 (7000h/80h)(0XE0)
DP_PF2 .set 225 ;頁 2 外設幀文件 (7080h/80h)(0XE1)
DP_PF3 .set 226 ;頁 3 外設幀文件 (7100h/80h)(0XE2)
DP_PF4 .set 227 ;頁 4 外設幀文件(7080h/80h)(0XE3)
DP_PF5 .set 228 ;頁 5 外設幀文件(7200h/80h)(0XE4)
DP_EVA .set 232 ;頁 0 事件管理器-EVA 文件 (7400h/80h)(0xE8)
DP_EVB .set 234 ;頁 0 事件管理器-EVB 文件 (7500h/80h)(0xE9)
;---------------------------------------------
; M A C R O - Definitions
;---------------------------------------------
SBIT0 .macro DMA,MASK ; Clear bit Macro
LACC DMA
AND #(0FFFFh-MASK)
SACL DMA
.endm
SBIT1 .macro DMA,MASK ; Set bit Macro
LACC DMA
OR #MASK
SACL DMA
.endm
KICK_DOG .macro ;Watchdog reset macro
LDP #00E0h
SPLK #05555h,WD_KEY
SPLK #0AAAAh,WD_KEY
LDP #0h
.endm
POINT_PG0 .macro
LDP #00h
.endm
POINT_B0 .macro
LDP #04h
.endm
POINT_PF1 .macro
LDP #0E0H
.endm
POINT_PF2 .macro
LDP #0E1h
.endm
POINT_EV .macro
LDP #0E8h
.endm
;=================================================================
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