?? st72324blk2.h

?? 汽車防盜器源程序
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/* System Integrity Control/Status Register */
STVD7_EXTERN volatile unsigned char SICSR @0x2b;
#define SICSR_WDGRF	0		/* Watchdog Reset Flag */
#define SICSR_WDGRF_OR	(1 << SICSR_WDGRF)
#define SICSR_LVDRF	4		/* LVD Reset Flag */
#define SICSR_LVDRF_OR	(1 << SICSR_LVDRF)
#define SICSR_AVDF	5		/* Voltage Detector Flag */
#define SICSR_AVDF_OR	(1 << SICSR_AVDF)
#define SICSR_AVDIE	6		/* Voltage Detector Interrupt */
#define SICSR_AVDIE_OR	(1 << SICSR_AVDIE)
#define SICSR_AVDS	7		/* Voltage Detection Selection */
#define SICSR_AVDS_OR	(1 << SICSR_AVDS)

/* Main Clock Control/Status Register */
STVD7_EXTERN volatile unsigned char MCCSR @0x2c;
#define MCCSR_OIF	0		/* Oscillator Interrupt Flag */
#define MCCSR_OIF_OR	(1 << MCCSR_OIF)
#define MCCSR_OIE	1		/* Oscillator Interrupt */
#define MCCSR_OIE_OR	(1 << MCCSR_OIE)
#define MCCSR_TB0	2		/* Time Base Control */
#define MCCSR_TB0_OR	(1 << MCCSR_TB0)
#define MCCSR_TB1	3		/* Time Base Control */
#define MCCSR_TB1_OR	(1 << MCCSR_TB1)
#define MCCSR_TB_OR	((1 << MCCSR_TB0)|(1 << MCCSR_TB1))
#define MCCSR_SMS	4		/* Slow Mode Select */
#define MCCSR_SMS_OR	(1 << MCCSR_SMS)
#define MCCSR_CP0	5		/* CPU Clock Prescaler */
#define MCCSR_CP0_OR	(1 << MCCSR_CP0)
#define MCCSR_CP1	6		/* CPU Clock Prescaler */
#define MCCSR_CP1_OR	(1 << MCCSR_CP1)
#define MCCSR_CP_OR	((1 << MCCSR_CP0)|(1 << MCCSR_CP1))
#define MCCSR_MCO	7		/* Main Clock Out */
#define MCCSR_MCO_OR	(1 << MCCSR_MCO)

/* MCC Beep Control Register */
STVD7_EXTERN volatile unsigned char MCCBCR @0x2d;
#define MCCBCR_BC0	0		/* Beep Control */
#define MCCBCR_BC0_OR	(1 << MCCBCR_BC0)
#define MCCBCR_BC1	1		/* Beep Control */
#define MCCBCR_BC1_OR	(1 << MCCBCR_BC1)
#define MCCBCR_BC_OR	((1 << MCCBCR_BC0)|(1 << MCCBCR_BC1))

/* 16-Bit Timer A */
/*****************************************************************/

/* Control Register 2 */
STVD7_EXTERN volatile unsigned char TACR2 @0x31;
#define TACR2_EXEDG	0		/* External Clock Edge */
#define TACR2_EXEDG_OR	(1 << TACR2_EXEDG)
#define TACR2_IEDG2	1		/* Input Edge 2 */
#define TACR2_IEDG2_OR	(1 << TACR2_IEDG2)
#define TACR2_CC0	2		/* Clock Control */
#define TACR2_CC0_OR	(1 << TACR2_CC0)
#define TACR2_CC1	3		/* Clock Control */
#define TACR2_CC1_OR	(1 << TACR2_CC1)
#define TACR2_CC_OR	((1 << TACR2_CC0)|(1 << TACR2_CC1))
#define TACR2_PWM	4		/* Pulse Width Modulation */
#define TACR2_PWM_OR	(1 << TACR2_PWM)
#define TACR2_OPM	5		/* One Pulse Mode */
#define TACR2_OPM_OR	(1 << TACR2_OPM)
#define TACR2_OC2E	6		/* Output Compare 2 Output Pin */
#define TACR2_OC2E_OR	(1 << TACR2_OC2E)
#define TACR2_OC1E	7		/* Output Compare 1 Output Pin */
#define TACR2_OC1E_OR	(1 << TACR2_OC1E)

/* Control Register 1 */
STVD7_EXTERN volatile unsigned char TACR1 @0x32;
#define TACR1_OLVL1	0		/* Output Level 1 */
#define TACR1_OLVL1_OR	(1 << TACR1_OLVL1)
#define TACR1_IEDG1	1		/* Input Edge 1 */
#define TACR1_IEDG1_OR	(1 << TACR1_IEDG1)
#define TACR1_OLVL2	2		/* Output Level 2 */
#define TACR1_OLVL2_OR	(1 << TACR1_OLVL2)
#define TACR1_FOLV1	3		/* Forced Output Compare 1 */
#define TACR1_FOLV1_OR	(1 << TACR1_FOLV1)
#define TACR1_FOLV2	4		/* Forced Output Compare 2 */
#define TACR1_FOLV2_OR	(1 << TACR1_FOLV2)
#define TACR1_TOIE	5		/* Timer Overflow Interrupt */
#define TACR1_TOIE_OR	(1 << TACR1_TOIE)
#define TACR1_OCIE	6		/* Output Compare Interrupt */
#define TACR1_OCIE_OR	(1 << TACR1_OCIE)
#define TACR1_ICIE	7		/* Input Capture Interrupt */
#define TACR1_ICIE_OR	(1 << TACR1_ICIE)

/* Control/Status Register */
STVD7_EXTERN volatile unsigned char TACSR @0x33;
#define TACSR_TIMD	2		/* Timer Disable */
#define TACSR_TIMD_OR	(1 << TACSR_TIMD)
#define TACSR_OCF2	3		/* Output Compare Flag 2 */
#define TACSR_OCF2_OR	(1 << TACSR_OCF2)
#define TACSR_ICF2	4		/* Input Capture Flag 2 */
#define TACSR_ICF2_OR	(1 << TACSR_ICF2)
#define TACSR_TOF	5		/* Timer Overflow */
#define TACSR_TOF_OR	(1 << TACSR_TOF)
#define TACSR_OCF1	6		/* Output Compare Flag 1 */
#define TACSR_OCF1_OR	(1 << TACSR_OCF1)
#define TACSR_ICF1	7		/* Input Capture Flag 1 */
#define TACSR_ICF1_OR	(1 << TACSR_ICF1)

/* Input Capture 1 Register */
STVD7_EXTERN volatile unsigned int TAIC1R @0x34;
/* Input Capture 1 High Register */
STVD7_EXTERN volatile unsigned char TAIC1HR @0x34;
/* Input Capture 1 Low Register */
STVD7_EXTERN volatile unsigned char TAIC1LR @0x35;

/* Output Compare 1 Register */
STVD7_EXTERN volatile unsigned int TAOC1R @0x36;
/* Output Compare 1 High Register */
STVD7_EXTERN volatile unsigned char TAOC1HR @0x36;
/* Output Compare 1 Low Register */
STVD7_EXTERN volatile unsigned char TAOC1LR @0x37;

/* Counter Register */
STVD7_EXTERN volatile unsigned int TACR @0x38;
/* Counter High Register */
STVD7_EXTERN volatile unsigned char TACHR @0x38;
/* Counter Low Register */
STVD7_EXTERN volatile unsigned char TACLR @0x39;

/* Alternate Counter Register */
STVD7_EXTERN volatile unsigned int TAACR @0x3a;
/* Alternate Counter High Register */
STVD7_EXTERN volatile unsigned char TAACHR @0x3a;
/* Alternate Counter Low Register */
STVD7_EXTERN volatile unsigned char TAACLR @0x3b;

/* Input Capture 2 Register */
STVD7_EXTERN volatile unsigned int TAIC2R @0x3c;
/* Input Capture 2 High Register */
STVD7_EXTERN volatile unsigned char TAIC2HR @0x3c;
/* Input Capture 2 Low Register */
STVD7_EXTERN volatile unsigned char TAIC2LR @0x3d;

/* Output Compare 2 Register */
STVD7_EXTERN volatile unsigned int TAOC2R @0x3e;
/* Output Compare 2 High Register */
STVD7_EXTERN volatile unsigned char TAOC2HR @0x3e;
/* Output Compare 2 Low Register */
STVD7_EXTERN volatile unsigned char TAOC2LR @0x3f;

/* 16-Bit Timer B */
/*****************************************************************/

/* Control Register 2 */
STVD7_EXTERN volatile unsigned char TBCR2 @0x41;
#define TBCR2_EXEDG	0		/* External Clock Edge */
#define TBCR2_EXEDG_OR	(1 << TBCR2_EXEDG)
#define TBCR2_IEDG2	1		/* Input Edge 2 */
#define TBCR2_IEDG2_OR	(1 << TBCR2_IEDG2)
#define TBCR2_CC0	2		/* Clock Control */
#define TBCR2_CC0_OR	(1 << TBCR2_CC0)
#define TBCR2_CC1	3		/* Clock Control */
#define TBCR2_CC1_OR	(1 << TBCR2_CC1)
#define TBCR2_CC_OR	((1 << TBCR2_CC0)|(1 << TBCR2_CC1))
#define TBCR2_PWM	4		/* Pulse Width Modulation */
#define TBCR2_PWM_OR	(1 << TBCR2_PWM)
#define TBCR2_OPM	5		/* One Pulse Mode */
#define TBCR2_OPM_OR	(1 << TBCR2_OPM)
#define TBCR2_OC2E	6		/* Output Compare 2 Output Pin */
#define TBCR2_OC2E_OR	(1 << TBCR2_OC2E)
#define TBCR2_OC1E	7		/* Output Compare 1 Output Pin */
#define TBCR2_OC1E_OR	(1 << TBCR2_OC1E)

/* Control Register 1 */
STVD7_EXTERN volatile unsigned char TBCR1 @0x42;
#define TBCR1_OLVL1	0		/* Output Level 1 */
#define TBCR1_OLVL1_OR	(1 << TBCR1_OLVL1)
#define TBCR1_IEDG1	1		/* Input Edge 1 */
#define TBCR1_IEDG1_OR	(1 << TBCR1_IEDG1)
#define TBCR1_OLVL2	2		/* Output Level 2 */
#define TBCR1_OLVL2_OR	(1 << TBCR1_OLVL2)
#define TBCR1_FOLV1	3		/* Forced Output Compare 1 */
#define TBCR1_FOLV1_OR	(1 << TBCR1_FOLV1)
#define TBCR1_FOLV2	4		/* Forced Output Compare 2 */
#define TBCR1_FOLV2_OR	(1 << TBCR1_FOLV2)
#define TBCR1_TOIE	5		/* Timer Overflow Interrupt */
#define TBCR1_TOIE_OR	(1 << TBCR1_TOIE)
#define TBCR1_OCIE	6		/* Output Compare Interrupt */
#define TBCR1_OCIE_OR	(1 << TBCR1_OCIE)
#define TBCR1_ICIE	7		/* Input Capture Interrupt */
#define TBCR1_ICIE_OR	(1 << TBCR1_ICIE)

/* Control/Status Register */
STVD7_EXTERN volatile unsigned char TBCSR @0x43;
#define TBCSR_TIMD	2		/* Timer Disable */
#define TBCSR_TIMD_OR	(1 << TBCSR_TIMD)
#define TBCSR_OCF2	3		/* Output Compare Flag 2 */
#define TBCSR_OCF2_OR	(1 << TBCSR_OCF2)
#define TBCSR_ICF2	4		/* Input Capture Flag 2 */
#define TBCSR_ICF2_OR	(1 << TBCSR_ICF2)
#define TBCSR_TOF	5		/* Timer Overflow */
#define TBCSR_TOF_OR	(1 << TBCSR_TOF)
#define TBCSR_OCF1	6		/* Output Compare Flag 1 */
#define TBCSR_OCF1_OR	(1 << TBCSR_OCF1)
#define TBCSR_ICF1	7		/* Input Capture Flag 1 */
#define TBCSR_ICF1_OR	(1 << TBCSR_ICF1)

/* Input Capture 1 Register */
STVD7_EXTERN volatile unsigned int TBIC1R @0x44;
/* Input Capture 1 High Register */
STVD7_EXTERN volatile unsigned char TBIC1HR @0x44;
/* Input Capture 1 Low Register */
STVD7_EXTERN volatile unsigned char TBIC1LR @0x45;

/* Output Compare 1 Register */
STVD7_EXTERN volatile unsigned int TBOC1R @0x46;
/* Output Compare 1 High Register */
STVD7_EXTERN volatile unsigned char TBOC1HR @0x46;
/* Output Compare 1 Low Register */
STVD7_EXTERN volatile unsigned char TBOC1LR @0x47;

/* Counter Register */
STVD7_EXTERN volatile unsigned int TBCR @0x48;
/* Counter High Register */
STVD7_EXTERN volatile unsigned char TBCHR @0x48;
/* Counter Low Register */
STVD7_EXTERN volatile unsigned char TBCLR @0x49;

/* Alternate Counter Register */
STVD7_EXTERN volatile unsigned int TBACR @0x4a;
/* Alternate Counter High Register */
STVD7_EXTERN volatile unsigned char TBACHR @0x4a;
/* Alternate Counter Low Register */
STVD7_EXTERN volatile unsigned char TBACLR @0x4b;

/* Input Capture 2 Register */
STVD7_EXTERN volatile unsigned int TBIC2R @0x4c;
/* Input Capture 2 High Register */
STVD7_EXTERN volatile unsigned char TBIC2HR @0x4c;
/* Input Capture 2 Low Register */
STVD7_EXTERN volatile unsigned char TBIC2LR @0x4d;

/* Output Compare 2 Register */
STVD7_EXTERN volatile unsigned int TBOC2R @0x4e;
/* Output Compare 2 High Register */
STVD7_EXTERN volatile unsigned char TBOC2HR @0x4e;
/* Output Compare 2 Low Register */
STVD7_EXTERN volatile unsigned char TBOC2LR @0x4f;

/* Serial Communications Interface (SCI) */
/*****************************************************************/

/* Status Register */
STVD7_EXTERN volatile unsigned char SCISR @0x50;
#define SCISR_PE	0		/* Parity Error */
#define SCISR_PE_OR	(1 << SCISR_PE)
#define SCISR_FE	1		/* Framing Error */
#define SCISR_FE_OR	(1 << SCISR_FE)
#define SCISR_NF	2		/* Noise Flag */
#define SCISR_NF_OR	(1 << SCISR_NF)
#define SCISR_OR	3		/* Overrun Error */
#define SCISR_OR_OR	(1 << SCISR_OR)
#define SCISR_IDLE	4		/* Idle line detect */
#define SCISR_IDLE_OR	(1 << SCISR_IDLE)
#define SCISR_RDRF	5		/* Received Data Ready Flag */
#define SCISR_RDRF_OR	(1 << SCISR_RDRF)
#define SCISR_TC	6		/* Transmission Complete */
#define SCISR_TC_OR	(1 << SCISR_TC)
#define SCISR_TDRE	7		/* Transmission Data Register Empty */
#define SCISR_TDRE_OR	(1 << SCISR_TDRE)

/* Data Register */
STVD7_EXTERN volatile unsigned char SCIDR @0x51;

/* Baud Rate Register */
STVD7_EXTERN volatile unsigned char SCIBRR @0x52;
#define SCIBRR_SCR0	0		/* Receiver Rate Divisor */
#define SCIBRR_SCR0_OR	(1 << SCIBRR_SCR0)
#define SCIBRR_SCR1	1		/* Receiver Rate Divisor */
#define SCIBRR_SCR1_OR	(1 << SCIBRR_SCR1)
#define SCIBRR_SCR2	2		/* Receiver Rate Divisor */
#define SCIBRR_SCR2_OR	(1 << SCIBRR_SCR2)
#define SCIBRR_SCR_OR	((1 << SCIBRR_SCR0)|(1 << SCIBRR_SCR1)\
		|(1 << SCIBRR_SCR2))
#define SCIBRR_SCT0	3		/* Transmitter Rate Divisor */
#define SCIBRR_SCT0_OR	(1 << SCIBRR_SCT0)
#define SCIBRR_SCT1	4		/* Transmitter Rate Divisor */
#define SCIBRR_SCT1_OR	(1 << SCIBRR_SCT1)
#define SCIBRR_SCT2	5		/* Transmitter Rate Divisor */
#define SCIBRR_SCT2_OR	(1 << SCIBRR_SCT2)
#define SCIBRR_SCT_OR	((1 << SCIBRR_SCT0)|(1 << SCIBRR_SCT1)\
		|(1 << SCIBRR_SCT2))
#define SCIBRR_SCP0	6		/* First SCI Prescaler */
#define SCIBRR_SCP0_OR	(1 << SCIBRR_SCP0)
#define SCIBRR_SCP1	7		/* First SCI Prescaler */
#define SCIBRR_SCP1_OR	(1 << SCIBRR_SCP1)
#define SCIBRR_SCP_OR	((1 << SCIBRR_SCP0)|(1 << SCIBRR_SCP1))

/* Control Register 1 */
STVD7_EXTERN volatile unsigned char SCICR1 @0x53;
#define SCICR1_PIE	0		/* Parity Interrupt Enable */
#define SCICR1_PIE_OR	(1 << SCICR1_PIE)
#define SCICR1_PS	1		/* Parity Selection */
#define SCICR1_PS_OR	(1 << SCICR1_PS)
#define SCICR1_PCE	2		/* Parity Control Enable */
#define SCICR1_PCE_OR	(1 << SCICR1_PCE)
#define SCICR1_WAKE	3		/* Wake-up Method */
#define SCICR1_WAKE_OR	(1 << SCICR1_WAKE)
#define SCICR1_M	4		/* Word Length */
#define SCICR1_M_OR	(1 << SCICR1_M)
#define SCICR1_SCID	5		/* Sci prescaler and outputs enable/disable bit */
#define SCICR1_SCID_OR	(1 << SCICR1_SCID)
#define SCICR1_T8	6		/* Transmit Data Bit 8 */
#define SCICR1_T8_OR	(1 << SCICR1_T8)
#define SCICR1_R8	7		/* Receive Data Bit 8 */
#define SCICR1_R8_OR	(1 << SCICR1_R8)

/* Control Register 2 */
STVD7_EXTERN volatile unsigned char SCICR2 @0x54;
#define SCICR2_SBK	0		/* Send Break */
#define SCICR2_SBK_OR	(1 << SCICR2_SBK)
#define SCICR2_RWU	1		/* Receiver Wake-up Mode */
#define SCICR2_RWU_OR	(1 << SCICR2_RWU)
#define SCICR2_RE	2		/* Receiver */
#define SCICR2_RE_OR	(1 << SCICR2_RE)
#define SCICR2_TE	3		/* Transmitter */
#define SCICR2_TE_OR	(1 << SCICR2_TE)
#define SCICR2_ILIE	4		/* Idle Line Interrupt */
#define SCICR2_ILIE_OR	(1 << SCICR2_ILIE)
#define SCICR2_RIE	5		/* Receiver Interrupt */
#define SCICR2_RIE_OR	(1 << SCICR2_RIE)
#define SCICR2_TCIE	6		/* Transmission Complete Interrupt */
#define SCICR2_TCIE_OR	(1 << SCICR2_TCIE)
#define SCICR2_TIE	7		/* Transmitter Interrupt */
#define SCICR2_TIE_OR	(1 << SCICR2_TIE)

/* Ext. Receive Prescaler Reg. */
STVD7_EXTERN volatile unsigned char SCIERPR @0x55;

/* Ext. Transmit Prescaler Reg. */
STVD7_EXTERN volatile unsigned char SCIETPR @0x57;

/* 10-Bit A/D Converter (ADC) */
/*****************************************************************/

/* Control/Status Register */
STVD7_EXTERN volatile unsigned char ADCCSR @0x70;
#define ADCCSR_CH0	0		/* Channel Selection */
#define ADCCSR_CH0_OR	(1 << ADCCSR_CH0)
#define ADCCSR_CH1	1		/* Channel Selection */
#define ADCCSR_CH1_OR	(1 << ADCCSR_CH1)
#define ADCCSR_CH2	2		/* Channel Selection */
#define ADCCSR_CH2_OR	(1 << ADCCSR_CH2)
#define ADCCSR_CH3	3		/* Channel Selection */
#define ADCCSR_CH3_OR	(1 << ADCCSR_CH3)
#define ADCCSR_CH_OR	((1 << ADCCSR_CH0)|(1 << ADCCSR_CH1)\
		|(1 << ADCCSR_CH2)|(1 << ADCCSR_CH3))
#define ADCCSR_ADON	5		/* A/D Start Converter */
#define ADCCSR_ADON_OR	(1 << ADCCSR_ADON)
#define ADCCSR_SPEED	6		/* A/D Clock Selection */
#define ADCCSR_SPEED_OR	(1 << ADCCSR_SPEED)
#define ADCCSR_EOC	7		/* End of Conversion */
#define ADCCSR_EOC_OR	(1 << ADCCSR_EOC)

/* Data High Register */
STVD7_EXTERN volatile unsigned char ADCDRH @0x71;

/* Data low Register */
STVD7_EXTERN volatile unsigned char ADCDRL @0x72;

#endif /* __ST72324BLK2__ */
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