;file name ml64000init.s
;data: 19/07/2005
;function:init system ,init stack and falsh sram 

  AREA boot, CODE, READONLY
  INCLUDE define.s
     
USERMODE  EQU 0x10
FIQMODE   EQU 0x11
IRQMODE   EQU 0x12
SVCMODE   EQU 0x13
ABORTMODE EQU 0x17
UNDEFMODE EQU 0x1b
MODEAMSK  EQU 0x1f 
NOINT	  EQU 0xc0
_ISR_STARTADDRESS EQU  0xD001F000

;Per defined stack

;USR_STACK     EQU    64
;FIQ_STACK     EQU    0
; IRQStackq    EQU    0
;SVCSTACK      EQU    32
;ABORTSRACK    EQU    32
;UNDEFSTACK    EQU    64
;MODEASTACK    EQU    32
;NOINT	  
SRAM_BASE    EQU  0xD0000000    ;Defined External SRAM
SRAM_SIZE    EQU  0x1FFF
SRAM_TOP     EQU  SRAM_BASE+SRAM_SIZE

RAM_BASE     EQU  0x10000000    ;Defined Internal RAM
RAM_SIZE     EQU  0x2000
RAM_TOP      EQU  RAM_BASE+RAM_SIZE
FLASH_BASE   EQU  0xC8000000    ;Defined External ROM
FLASH_SIZE   EQU  0x80000
FLASH_TOP    EQU  FLASH_BASE+FLASH_SIZE

SDRAM_BASE   EQU  0xC0000000    ;External SDRAM 
SDRAM_SIZE   EQU  0x140000
SDRAM_TOP    EQU  SDRAM_BASE+SDRAM_SIZE

;RMPCON_BASE  EQU 

Remap_Base   EQU        0xB8000010    ;address of map controller base 
Romac_Base   EQU        0x78100004	  ;address of flash controller base
Ramac_Base   EQU 	    0x78100008	  ;address of ram controller base 


;initlation system and hardware clock 


       MACRO 
$HandlerLabel HANDLER $HandleLabel

$HandlerLabel
        sub     sp,sp,#4  ;store jump Address
        stmfd    sp!,{r0}
        ldr      r0,=$HandleLabel
        ldr      r0,[r0]
        str      r0,[sp,#4]
        ldmfd    sp!,{r0,pc}
        MEND
                   
                  
 ;******************************************
 ; Vectors exception
 ;*****************************************
ENTRY       
     ;ldr	pc, =0x0c000004			;handlerUndef
     ;ldr	pc, =0x0c000008			;SWI interrupt handler
     ;ldr	pc, =0x0c00000c			;handlerPAbort
     ;ldr	pc, =0x0c000010			;handlerDAbort
     ; b .							;handlerReserved
     ;ldr	pc, =0x0c000018
     ;ldr	pc, =0x0c00001c               ;for debug
  b Reset_Handler
  b HandlerUndef                    ;handlerUndef
  b HandlerSWI                 ;SWI interrupt handler
  b HandlerPabort              ;handlerPAbort
  b HandlerDabort              ;handlerDAbort
  b .                          ;handlerReserved
  b HandlerIRQ
  b HandlerFIQ
  
                       
Reset_Handler 
       
; enter  IRQ mode and set up the IRQ stack pointer
        MOV     R0, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; no interrupts
        MSR     CPSR_c, R0
        LDR     R13, =IRQStack ; set IRQ mode stack.
        
; - Set up  Fast Interrupt Mode and set FIQ Mode Stack
        MOV     R0, #Mode_FIQ:OR:F_Bit ; no interrupts
        MSR     CPSR_c, R0
        LDR     R13, =FIQStack ; set IRQ mode stack.
                
; - Set up Abort Mode and set Abort Mode Stack 
        MOV     R0, #Mode_ABT:OR:I_Bit:OR:F_Bit ; no interrupts
        MSR     CPSR_c, R0
        LDR     R13, =AbortStack ; set IRQ mode stack.   
        
; - Set up Undefined Instruction Mode and set Undef Mode Stack 
        MOV     R0, #Mode_UND:OR:I_Bit:OR:F_Bit ; no interrupts
        MSR     CPSR_c, R0
        LDR     R13, =UndefStack ; 

; - set up the SVC stack pointer last and return to SVC mode
        MOV     R0, #Mode_SVC:OR:F_Bit ; no interrupts
        MSR     CPSR_c, R0
        LDR     R13, =SVCStack ; set SVC mode STACK.                                             
;enable external bus function(P1OA[14--0])
  LDR  R0,=GPCTL
  LDRH R1,[R0]
  ORR R1,R1,#0x5  ;ENABLE A19 A20
  STRH R1,[R0]

  LDR R0,=BWC
  MOV R1,#0xA8
  STR R1,[R0]
  
  ; init external ROM falsh

  LDR R0,=Romac_Base
; MOV R1,#0x01
  MOV R1,#0x02
  STR R1, [R0]
  
;Init external SRAM

 LDR R0, =Ramac_Base
 MOV R1,#0X02
 STR R1, [R0]



;REMAP
; MOV R1,#0x40000000 ;internal ram Address of start
; MOV R2,#vectors
; ldmia r2,{r3-r10}
;;stmia r1,{r3-r10}
; ldmia r2,{r3-r10}
; stmia r1,{r3-r10}

; MOV R1,#RMPCON_BASE
; MOV R2,#0x02
; LDR R1,[R2]


  
; --- initialize memory required by C code

       IMPORT  |Image$$RO$$Limit|      ; end of ROM code (=start of ROM data)
       IMPORT  |Image$$RW$$Base|       ; base of RAM to initialize
       IMPORT  |Image$$ZI$$Base|       ; base and limit of area
       IMPORT  |Image$$ZI$$Limit|      ; to zero initialize

        LDR     r0, =|Image$$RO$$Limit| ; get pointer to ROM data
        LDR     r1, =|Image$$RW$$Base|  ; and RAM copy
        LDR     r3, =|Image$$ZI$$Base|  ; zero init base => top of initialized data
        CMP     r0, r1  ; check that they are different
        BEQ     %F1         
0       CMP     r1, r3  ; copy init data
        LDRCC   r2, [r0], #4
        STRCC   r2, [r1], #4
        BCC     %B0
1       LDR     r1, =|Image$$ZI$$Limit| ; top of zero init segment
        MOV     r2, #0
2       CMP     r3, r1  ; zero init
        STRCC   r2, [r3], #4
        BCC     %B2
  
  IMPORT  main
  LDR  PC, = main
END_LOOP

        B   END_LOOP


  LTORG 
  
     	
HandlerFIQ	    HANDLER HandleFIQ
HandlerIRQ	    HANDLER HandleIRQ
HandlerUndef   HANDLER HandleUndef
HandlerSWI	    HANDLER HandleSWI
HandlerDabort	HANDLER HandleDabort
HandlerPabort	HANDLER HandlePabort       
        
      AREA RamData, DATA, READWRITE

	^	(_ISR_STARTADDRESS-0x500)
				
UserStack	#	256	;c1(c7)ffa00
SVCStack	#	256	;c1(c7)ffb00
UndefStack	#	256	;c1(c7)ffc00
AbortStack	#	256	;c1(c7)ffd00
IRQStack	#	256	;c1(c7)ffe00
FIQStack	#	0	;c1(c7)fff00

	^	_ISR_STARTADDRESS
HandleReset		#	4
HandleUndef		#	4
HandleSWI		#	4
HandlePabort	#	4
HandleDabort	#	4
HandleReserved	#	4
HandleIRQ		#	4
HandleFIQ		#	4

   
        END