?? median_filter.v
字號(hào):
// +FHDR------------------------------------------------------------------------
// Copyright (c) 2004, pudn ASIC.
// pudn ASIC Confidential Proprietary
// -----------------------------------------------------------------------------
// FILE NAME : median_filter.v
// TYPE : parameter
// DEPARTMENT : pudn ASIC
// AUTHOR : Liu Yuxuan
// AUTHOR' EMAIL : liuyuxuan@pudn.com
// -----------------------------------------------------------------------------
// Release history
// VERSION Date AUTHOR DESCRIPTION
// 0.0 12 Jun 2006, Liu Yuxuan (Create)
// -----------------------------------------------------------------------------
// KEYWORDS : Digital Video Processer, Noise Reduction, Median Filter
// -----------------------------------------------------------------------------
// PURPOSE :
// This module is part of the median filter circuit. This file
// generates the 3*3 median filter.
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : VA UNITS
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy :
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Scan Methodology :
// Instantiations :
// Other :
// -FHDR------------------------------------------------------------------------
`resetall
`timescale 1ns/1ps
module median_filter(
clk,
rst_n,
hs,
vs,
hde,
vde,
edge_here,
filter_sel,
mdf_a11,
mdf_a12,
mdf_a13,
mdf_a21,
mdf_a22,
mdf_a23,
mdf_a31,
mdf_a32,
mdf_a33,
des_data_y,
des_data_uv,
hs_out,
vs_out,
hde_out,
vde_out
);
// Internal Declarations
input clk;
input rst_n;
input hs;
input vs;
input hde;
input vde;
input edge_here;
input [1:0] filter_sel;
input [15:0] mdf_a11;
input [15:0] mdf_a12;
input [15:0] mdf_a13;
input [15:0] mdf_a21;
input [15:0] mdf_a22;
input [15:0] mdf_a23;
input [15:0] mdf_a31;
input [15:0] mdf_a32;
input [15:0] mdf_a33;
output [7:0] des_data_y;
output [7:0] des_data_uv;
output hs_out;
output vs_out;
output hde_out;
output vde_out;
wire clk;
wire rst_n;
wire hs;
wire vs;
wire hde;
wire vde;
wire edge_here;
wire [1:0] filter_sel;
wire [15:0] mdf_a11;
wire [15:0] mdf_a12;
wire [15:0] mdf_a13;
wire [15:0] mdf_a21;
wire [15:0] mdf_a22;
wire [15:0] mdf_a23;
wire [15:0] mdf_a31;
wire [15:0] mdf_a32;
wire [15:0] mdf_a33;
wire [7:0] des_data_y;
wire [7:0] des_data_uv;
reg hs_out;
reg vs_out;
reg hde_out;
reg vde_out;
// ### Please start your Verilog code here ###
reg [15:0] mdf_a22_d1, mdf_a22_d2, mdf_a22_d3;
reg [15:0] mdf_a22_d4, mdf_a22_d5, mdf_a22_d6;
wire [7:0] max_1_y, max_2_y, max_3_y;
wire [7:0] min_1_y, min_2_y, min_3_y;
wire [7:0] median_1_y, median_2_y, median_3_y;
wire [7:0] max_1_uv, max_2_uv, max_3_uv;
wire [7:0] min_1_uv, min_2_uv, min_3_uv;
wire [7:0] median_1_uv, median_2_uv, median_3_uv;
wire [7:0] max_y, min_y;
wire [7:0] max_uv, min_uv;
wire [7:0] des_data_y_tmp;
wire [7:0] des_data_uv_tmp;
wire noise_here_y;
wire noise_here_uv;
reg hs_d1, hs_d2, hs_d3, hs_d4, hs_d5;
reg vs_d1, vs_d2, vs_d3, vs_d4, vs_d5;
reg hde_d1, hde_d2, hde_d3, hde_d4, hde_d5;
reg vde_d1, vde_d2, vde_d3, vde_d4, vde_d5;
comparator_mdf comparator_3x3_1_y(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (mdf_a11[15:8]),
.input_2 (mdf_a12[15:8]),
.input_3 (mdf_a13[15:8]),
.max (max_1_y),
.min (min_1_y),
.median (median_1_y)
);
comparator_mdf comparator_3x3_2_y(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (mdf_a21[15:8]),
.input_2 (mdf_a22[15:8]),
.input_3 (mdf_a23[15:8]),
.max (max_2_y),
.min (min_2_y),
.median (median_2_y)
);
comparator_mdf comparator_3x3_3_y(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (mdf_a31[15:8]),
.input_2 (mdf_a32[15:8]),
.input_3 (mdf_a33[15:8]),
.max (max_3_y),
.min (min_3_y),
.median (median_3_y)
);
comparator_mdf comparator_3x3_final_max_y(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (max_1_y),
.input_2 (max_2_y),
.input_3 (max_3_y),
.max (max_y),
.min (),
.median ()
);
comparator_mdf comparator_3x3_final_min_y(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (min_1_y),
.input_2 (min_2_y),
.input_3 (min_3_y),
.max (),
.min (min_y),
.median ()
);
comparator_mdf comparator_3x3_final_median_y(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (median_1_y),
.input_2 (median_2_y),
.input_3 (median_3_y),
.max (),
.min (),
.median (des_data_y_tmp)
);
comparator_mdf comparator_3x3_1_uv(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (mdf_a11[7:0]),
.input_2 (mdf_a12[7:0]),
.input_3 (mdf_a13[7:0]),
.max (max_1_uv),
.min (min_1_uv),
.median (median_1_uv)
);
comparator_mdf comparator_3x3_2_uv(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (mdf_a21[7:0]),
.input_2 (mdf_a22[7:0]),
.input_3 (mdf_a23[7:0]),
.max (max_2_uv),
.min (min_2_uv),
.median (median_2_uv)
);
comparator_mdf comparator_3x3_3_uv(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (mdf_a31[7:0]),
.input_2 (mdf_a32[7:0]),
.input_3 (mdf_a33[7:0]),
.max (max_3_uv),
.min (min_3_uv),
.median (median_3_uv)
);
comparator_mdf comparator_3x3_final_max_uv(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (max_1_uv),
.input_2 (max_2_uv),
.input_3 (max_3_uv),
.max (max_uv),
.min (),
.median ()
);
comparator_mdf comparator_3x3_final_min_uv(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (min_1_uv),
.input_2 (min_2_uv),
.input_3 (min_3_uv),
.max (),
.min (min_uv),
.median ()
);
comparator_mdf comparator_3x3_final_median_uv(
.clk (clk),
.rst_n (rst_n),
.filter_sel (filter_sel),
.input_1 (median_1_uv),
.input_2 (median_2_uv),
.input_3 (median_3_uv),
.max (),
.min (),
.median (des_data_uv_tmp)
);
assign noise_here_y=((mdf_a22_d6[15:8]==max_y)||(mdf_a22_d6[15:8]==min_y))&&(~edge_here);
assign noise_here_uv=((mdf_a22_d6[7:0]==max_uv)||(mdf_a22_d6[7:0]==min_uv))&&(~edge_here);
assign des_data_y=noise_here_y?des_data_y_tmp:mdf_a22_d6[15:8];
assign des_data_uv=noise_here_uv?des_data_uv_tmp:mdf_a22_d6[7:0];
//this always block initializes mdf_a22_d* and generates
//correct mdf_a22_d*
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
mdf_a22_d1<=16'b0;
mdf_a22_d2<=16'b0;
mdf_a22_d3<=16'b0;
mdf_a22_d4<=16'b0;
mdf_a22_d5<=16'b0;
mdf_a22_d6<=16'b0;
end
else
begin
mdf_a22_d1<=mdf_a22;
mdf_a22_d2<=mdf_a22_d1;
mdf_a22_d3<=mdf_a22_d2;
mdf_a22_d4<=mdf_a22_d3;
mdf_a22_d5<=mdf_a22_d4;
mdf_a22_d6<=mdf_a22_d5;
end//else if !rst_n
end//always
//this always block initializes hs_out, vs_out and generates
//hs_out, vs_out
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
hs_d1<=1'b0;
hs_d2<=1'b0;
hs_d3<=1'b0;
hs_d4<=1'b0;
hs_d5<=1'b0;
hs_out<=1'b0;
vs_d1<=1'b0;
vs_d2<=1'b0;
vs_d3<=1'b0;
vs_d4<=1'b0;
vs_d5<=1'b0;
vs_out<=1'b0;
end
else
begin
hs_d1<=hs;
hs_d2<=hs_d1;
hs_d3<=hs_d2;
hs_d4<=hs_d3;
hs_d5<=hs_d4;
hs_out<=hs_d5;
vs_d1<=vs;
vs_d2<=vs_d1;
vs_d3<=vs_d2;
vs_d4<=vs_d3;
vs_d5<=vs_d4;
vs_out<=vs_d5;
end//else if !rst_n
end//always
//this always block initializes hde_out, vde_out and generates
//correct hde_out, vde_out
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
hde_d1<=1'b0;
hde_d2<=1'b0;
hde_d3<=1'b0;
hde_d4<=1'b0;
hde_d5<=1'b0;
hde_out<=1'b0;
vde_d1<=1'b0;
vde_d2<=1'b0;
vde_d3<=1'b0;
vde_d4<=1'b0;
vde_d5<=1'b0;
vde_out<=1'b0;
end
else
begin
hde_d1<=hde;
hde_d2<=hde_d1;
hde_d3<=hde_d2;
hde_d4<=hde_d3;
hde_d5<=hde_d4;
hde_out<=hde_d5;
vde_d1<=vde;
vde_d2<=vde_d1;
vde_d3<=vde_d2;
vde_d4<=vde_d3;
vde_d5<=vde_d4;
vde_out<=vde_d5;
end//else if !rst_n
end//always
endmodule?? 快捷鍵說(shuō)明
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