Release 6.2i Par G.28Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.HP-C15EA608E392::  Sun Dec 07 12:10:59 2008C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 minute1_map.ncd
minute1.ncd minute1.pcf Constraints file: minute1.pcfLoading device database for application Par from file "minute1_map.ncd".   "minute1" is an NCD, version 2.38, device xc2s50e, package pq208, speed -6Loading device for application Par from file '2s50e.nph' in environment
C:/Xilinx.Device speed data version:  PRODUCTION 1.17 2003-12-13.Device utilization summary:   Number of External GCLKIOBs         1 out of 4      25%   Number of External IOBs            10 out of 142     7%      Number of LOCed External IOBs    0 out of 10      0%   Number of SLICEs                   10 out of 768     1%   Number of GCLKs                     1 out of 4      25%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Phase 1.1Phase 1.1 (Checksum:9896f1) REAL time: 0 secs Phase 2.23Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs Phase 3.3Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8.Phase 5.8 (Checksum:98b6b9) REAL time: 0 secs Phase 6.5Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file minute1.ncd.Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 67 unrouted;       REAL time: 0 secs Phase 2: 60 unrouted;       REAL time: 0 secs Phase 3: 10 unrouted;       REAL time: 0 secs Phase 4: 0 unrouted;       REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics.**************************Generating Clock Report**************************+----------------------------+----------+--------+------------+-------------+|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|+----------------------------+----------+--------+------------+-------------+|        clkm_BUFGP          |  Global  |    7   |  0.180     |  0.531      |+----------------------------+----------+--------+------------+-------------+   The Delay Summary Report   The SCORE FOR THIS DESIGN is: 100The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.783   The MAXIMUM PIN DELAY IS:                               1.936   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.101   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------          47          20           0           0           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 0 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  48 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Writing design to file minute1.ncd.PAR done.