-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:31:53 2008

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY dd IS
END dd;

ARCHITECTURE testbench_arch OF dd IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\vhdl\shuzizhong\shuzizhong\dd.ano";
	COMPONENT alarm1
		PORT (
			reset : In  std_logic;
			Min1 : In  std_logic_vector (3 DOWNTO 0);
			min2 : In  std_logic_vector (3 DOWNTO 0);
			Alarm : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL Min1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL min2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL Alarm : std_logic;

BEGIN
	UUT : alarm1
	PORT MAP (
		reset => reset,
		Min1 => Min1,
		min2 => min2,
		Alarm => Alarm
	);

	PROCESS -- Annotate outputs process
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_Alarm(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",Alarm,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Alarm);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_Alarm(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '1';
		Min1 <= transport std_logic_vector'("0001"); --1
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		Min1 <= transport std_logic_vector'("0101"); --5
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 200 ns; -- Time=400 ns
		Min1 <= transport std_logic_vector'("0101"); --5
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 200 ns; -- Time=600 ns
		Min1 <= transport std_logic_vector'("0000"); --0
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 1500 ns; -- Time=2100 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION alarm1_cfg OF dd IS
	FOR testbench_arch
	END FOR;
END alarm1_cfg;