-      2     -    A    06        OR2                2    1    1    0  |LPM_ADD_SUB:19|addcore:adder|:92


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                         e:\edashi\sin\adder6b.rpt
adder6b

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       8/ 96(  8%)     4/ 48(  8%)     1/ 48(  2%)    3/16( 18%)      6/16( 37%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         e:\edashi\sin\adder6b.rpt
adder6b

** EQUATIONS **

A6B0     : INPUT;
A6B1     : INPUT;
A6B2     : INPUT;
A6B3     : INPUT;
A6B4     : INPUT;
A6B5     : INPUT;
B6B0     : INPUT;
B6B1     : INPUT;
B6B2     : INPUT;
B6B3     : INPUT;
B6B4     : INPUT;
B6B5     : INPUT;

-- Node name is 'S6B0' 
-- Equation name is 'S6B0', type is output 
S6B0     =  _LC8_A22;

-- Node name is 'S6B1' 
-- Equation name is 'S6B1', type is output 
S6B1     =  _LC5_A22;

-- Node name is 'S6B2' 
-- Equation name is 'S6B2', type is output 
S6B2     =  _LC6_A6;

-- Node name is 'S6B3' 
-- Equation name is 'S6B3', type is output 
S6B3     =  _LC1_A6;

-- Node name is 'S6B4' 
-- Equation name is 'S6B4', type is output 
S6B4     =  _LC5_A6;

-- Node name is 'S6B5' 
-- Equation name is 'S6B5', type is output 
S6B5     =  _LC2_A6;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ001);
  _EQ001 =  A6B1 &  B6B1
         #  A6B0 &  A6B1 &  B6B0
         #  A6B0 &  B6B0 &  B6B1;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC3_A6', type is buried 
_LC3_A6  = LCELL( _EQ002);
  _EQ002 =  A6B2 &  _LC6_A22
         #  B6B2 &  _LC6_A22
         #  A6B2 &  B6B2;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC4_A6', type is buried 
_LC4_A6  = LCELL( _EQ003);
  _EQ003 =  B6B3 &  _LC3_A6
         #  A6B3 &  _LC3_A6
         #  A6B3 &  B6B3;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|pcarry4' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_A6', type is buried 
_LC7_A6  = LCELL( _EQ004);
  _EQ004 =  B6B4 &  _LC4_A6
         #  A6B4 &  _LC4_A6
         #  A6B4 &  B6B4;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|:81' from file "addcore.tdf" line 315, column 26
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ005);
  _EQ005 =  A6B0 & !B6B0
         # !A6B0 &  B6B0;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|:88' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_A22', type is buried 
_LC5_A22 = LCELL( _EQ006);
  _EQ006 =  A6B0 &  A6B1 &  B6B0 &  B6B1
         # !A6B0 &  A6B1 & !B6B1
         #  A6B1 & !B6B0 & !B6B1
         # !A6B0 & !A6B1 &  B6B1
         # !A6B1 & !B6B0 &  B6B1
         #  A6B0 & !A6B1 &  B6B0 & !B6B1;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|:89' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_A6', type is buried 
_LC6_A6  = LCELL( _EQ007);
  _EQ007 =  A6B2 &  B6B2 &  _LC6_A22
         # !A6B2 & !B6B2 &  _LC6_A22
         #  A6B2 & !B6B2 & !_LC6_A22
         # !A6B2 &  B6B2 & !_LC6_A22;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|:90' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_A6', type is buried 
_LC1_A6  = LCELL( _EQ008);
  _EQ008 =  A6B3 &  B6B3 &  _LC3_A6
         # !A6B3 & !B6B3 &  _LC3_A6
         # !A6B3 &  B6B3 & !_LC3_A6
         #  A6B3 & !B6B3 & !_LC3_A6;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|:91' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_A6', type is buried 
_LC5_A6  = LCELL( _EQ009);
  _EQ009 =  A6B4 &  B6B4 &  _LC4_A6
         # !A6B4 & !B6B4 &  _LC4_A6
         # !A6B4 &  B6B4 & !_LC4_A6
         #  A6B4 & !B6B4 & !_LC4_A6;

-- Node name is '|LPM_ADD_SUB:19|addcore:adder|:92' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = LCELL( _EQ010);
  _EQ010 =  A6B5 &  B6B5 &  _LC7_A6
         # !A6B5 & !B6B5 &  _LC7_A6
         # !A6B5 &  B6B5 & !_LC7_A6
         #  A6B5 & !B6B5 & !_LC7_A6;



Project Information                                  e:\edashi\sin\adder6b.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 10,640K