?? fshow.rpt
字號:
D15 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
D16 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
D17 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 1/2 0/2 8/22( 36%)
D19 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 4/22( 18%)
D20 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 0/22( 0%)
D21 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
D22 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 0/2 3/22( 13%)
D23 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
D24 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 0/2 10/22( 45%)
E24 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 0/22( 0%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 4/6 ( 66%)
Total I/O pins used: 26/96 ( 27%)
Total logic cells used: 184/1152 ( 15%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.01/4 ( 75%)
Total fan-in: 554/4608 ( 12%)
Total input pins required: 4
Total input I/O cell registers required: 0
Total output pins required: 26
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 184
Total flipflops required: 56
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 18/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 8 8 7 0 8 8 8 0 0 0 0 0 0 8 8 0 8 0 0 8 8 0 8 1 96/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 8 0 8 0 0 0 19/0
D: 0 0 0 0 1 0 0 0 0 0 0 0 0 0 8 8 3 8 0 7 1 8 8 8 8 68/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 8 8 7 1 8 8 8 0 0 0 0 0 3 16 16 3 16 0 15 9 24 8 16 10 184/0
Device-Specific Information: f:\sin\fshow.rpt
fshow
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT G 0 0 0 0 clk0
56 - - - -- INPUT G 0 0 0 0 clk1
125 - - - -- INPUT G 0 0 0 0 clk2
55 - - - -- INPUT G 0 0 0 0 clk3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\sin\fshow.rpt
fshow
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
22 - - D -- OUTPUT 0 1 0 0 f0
20 - - D -- OUTPUT 0 1 0 0 f1
130 - - - 15 OUTPUT 0 1 0 0 f2
18 - - D -- OUTPUT 0 1 0 0 f3
43 - - - 18 OUTPUT 0 1 0 0 f4
11 - - C -- OUTPUT 0 1 0 0 f5
92 - - C -- OUTPUT 0 1 0 0 f6
13 - - C -- OUTPUT 0 1 0 0 f7
90 - - C -- OUTPUT 0 1 0 0 f8
91 - - C -- OUTPUT 0 1 0 0 f9
12 - - C -- OUTPUT 0 1 0 0 f10
14 - - C -- OUTPUT 0 1 0 0 f11
9 - - B -- OUTPUT 0 1 0 0 f12
135 - - - 19 OUTPUT 0 0 0 0 f13
132 - - - 16 OUTPUT 0 0 0 0 f14
116 - - - 04 OUTPUT 0 0 0 0 f15
23 - - D -- OUTPUT 0 1 0 0 m40
19 - - D -- OUTPUT 0 1 0 0 m41
21 - - D -- OUTPUT 0 1 0 0 m42
17 - - D -- OUTPUT 0 1 0 0 m43
122 - - - 13 OUTPUT 0 1 0 0 m44
88 - - D -- OUTPUT 0 1 0 0 m45
98 - - B -- OUTPUT 0 1 0 0 m46
10 - - B -- OUTPUT 0 1 0 0 m47
99 - - B -- OUTPUT 0 1 0 0 m48
95 - - B -- OUTPUT 0 1 0 0 m49
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\sin\fshow.rpt
fshow
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 06 OR2 0 3 0 1 |LPM_ADD_SUB:189|addcore:adder|:95
- 2 - B 06 OR2 0 4 0 2 |LPM_ADD_SUB:189|addcore:adder|:99
- 5 - B 07 AND2 0 2 0 2 |LPM_ADD_SUB:189|addcore:adder|:103
- 6 - B 07 AND2 0 2 0 1 |LPM_ADD_SUB:189|addcore:adder|:107
- 8 - B 06 OR2 0 3 0 1 |LPM_ADD_SUB:261|addcore:adder|pcarry5
- 1 - B 06 OR2 0 4 0 2 |LPM_ADD_SUB:261|addcore:adder|pcarry6
- 7 - B 07 OR2 0 2 0 2 |LPM_ADD_SUB:261|addcore:adder|pcarry7
- 8 - B 07 OR2 0 2 0 1 |LPM_ADD_SUB:261|addcore:adder|pcarry8
- 7 - B 02 OR2 0 3 0 1 |LPM_ADD_SUB:584|addcore:adder|pcarry4
- 6 - B 02 OR2 0 4 0 2 |LPM_ADD_SUB:584|addcore:adder|pcarry5
- 1 - B 02 OR2 0 2 0 2 |LPM_ADD_SUB:584|addcore:adder|pcarry6
- 1 - B 08 AND2 0 2 0 2 |LPM_ADD_SUB:584|addcore:adder|:103
- 3 - B 08 AND2 0 2 0 1 |LPM_ADD_SUB:584|addcore:adder|:107
- 2 - B 02 OR2 0 4 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry5
- 4 - B 08 OR2 0 2 0 2 |LPM_ADD_SUB:656|addcore:adder|pcarry6
- 8 - B 02 AND2 0 3 0 1 |LPM_ADD_SUB:656|addcore:adder|:91
- 5 - B 08 AND2 0 2 0 2 |LPM_ADD_SUB:656|addcore:adder|:103
- 7 - B 08 AND2 0 2 0 1 |LPM_ADD_SUB:656|addcore:adder|:107
- 1 - D 21 OR2 0 2 0 2 |LPM_ADD_SUB:979|addcore:adder|pcarry5
- 7 - B 21 OR2 0 2 0 2 |LPM_ADD_SUB:979|addcore:adder|pcarry7
- 8 - B 21 OR2 0 2 0 1 |LPM_ADD_SUB:979|addcore:adder|pcarry8
- 3 - D 19 OR2 0 3 0 1 |LPM_ADD_SUB:979|addcore:adder|:87
- 7 - D 21 OR2 0 4 0 2 |LPM_ADD_SUB:979|addcore:adder|:91
- 6 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:979|addcore:adder|:99
- 8 - D 21 OR2 0 3 0 1 |LPM_ADD_SUB:1051|addcore:adder|pcarry3
- 6 - D 21 OR2 0 4 0 2 |LPM_ADD_SUB:1051|addcore:adder|:91
- 4 - D 21 AND2 0 2 0 2 |LPM_ADD_SUB:1051|addcore:adder|:95
- 3 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:1051|addcore:adder|:99
- 5 - B 21 AND2 0 2 0 2 |LPM_ADD_SUB:1051|addcore:adder|:103
- 4 - B 21 AND2 0 2 0 1 |LPM_ADD_SUB:1051|addcore:adder|:107
- 7 - D 23 OR2 0 3 0 1 |LPM_ADD_SUB:1374|addcore:adder|pcarry2
- 5 - D 23 OR2 0 2 0 2 |LPM_ADD_SUB:1374|addcore:adder|pcarry4
- 4 - B 17 OR2 0 2 0 2 |LPM_ADD_SUB:1374|addcore:adder|pcarry5
- 8 - B 17 OR2 0 2 0 2 |LPM_ADD_SUB:1374|addcore:adder|pcarry6
- 4 - B 14 OR2 0 2 0 2 |LPM_ADD_SUB:1374|addcore:adder|pcarry7
- 5 - B 14 OR2 0 2 0 1 |LPM_ADD_SUB:1374|addcore:adder|pcarry8
- 3 - D 23 OR2 0 4 0 2 |LPM_ADD_SUB:1374|addcore:adder|:87
- 8 - D 23 AND2 0 3 0 1 |LPM_ADD_SUB:1446|addcore:adder|:83
- 4 - D 23 AND2 0 4 0 2 |LPM_ADD_SUB:1446|addcore:adder|:87
- 1 - D 23 AND2 0 2 0 2 |LPM_ADD_SUB:1446|addcore:adder|:91
- 5 - B 17 AND2 0 2 0 2 |LPM_ADD_SUB:1446|addcore:adder|:95
- 6 - B 17 AND2 0 2 0 2 |LPM_ADD_SUB:1446|addcore:adder|:99
- 2 - B 17 AND2 0 2 0 2 |LPM_ADD_SUB:1446|addcore:adder|:103
- 6 - B 14 AND2 0 2 0 1 |LPM_ADD_SUB:1446|addcore:adder|:107
- 1 - D 22 OR2 0 4 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry1
- 8 - B 03 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry2
- 3 - B 03 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry3
- 4 - B 04 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry4
- 6 - B 04 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry5
- 7 - B 04 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry6
- 3 - B 04 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|pcarry7
- 2 - D 22 OR2 0 4 0 3 |LPM_ADD_SUB:2573|addcore:adder|:133
- 6 - B 03 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|:134
- 4 - B 03 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|:135
- 7 - B 03 OR2 0 3 0 2 |LPM_ADD_SUB:2573|addcore:adder|:136
- 5 - B 04 OR2 0 3 0 3 |LPM_ADD_SUB:2573|addcore:adder|:137
- 1 - B 04 OR2 0 3 0 3 |LPM_ADD_SUB:2573|addcore:adder|:138
- 2 - B 04 OR2 0 3 0 3 |LPM_ADD_SUB:2573|addcore:adder|:139
- 4 - B 15 OR2 0 3 0 3 |LPM_ADD_SUB:2573|addcore:adder|:140
- 6 - D 19 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry1
- 4 - D 19 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry2
- 2 - D 16 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry3
- 4 - D 16 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry4
- 3 - D 17 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry5
- 3 - B 23 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry6
- 2 - B 15 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|pcarry7
- 8 - D 22 OR2 0 3 0 1 |LPM_ADD_SUB:2574|addcore:adder|:80
- 6 - D 22 OR2 0 3 0 1 |LPM_ADD_SUB:2574|addcore:adder|:129
- 5 - D 22 OR2 s 0 4 0 2 |LPM_ADD_SUB:2574|addcore:adder|~142~1
- 5 - D 19 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|:143
- 4 - D 14 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|:144
- 1 - D 16 OR2 0 3 0 2 |LPM_ADD_SUB:2574|addcore:adder|:145
- 7 - D 17 OR2 s 0 2 0 2 |LPM_ADD_SUB:2574|addcore:adder|~146~1
- 4 - B 23 OR2 s 0 2 0 2 |LPM_ADD_SUB:2574|addcore:adder|~147~1
- 1 - B 24 OR2 s 0 2 0 2 |LPM_ADD_SUB:2574|addcore:adder|~148~1
- 3 - B 15 OR2 s 0 2 0 2 |LPM_ADD_SUB:2574|addcore:adder|~149~1
- 1 - D 24 OR2 0 4 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry1
- 6 - D 14 OR2 0 3 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry2
- 7 - D 14 OR2 0 3 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry3
- 2 - D 14 OR2 0 3 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry4
- 2 - D 17 OR2 0 4 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry5
- 8 - B 23 OR2 0 4 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry6
- 1 - B 23 OR2 0 4 0 2 |LPM_ADD_SUB:2575|addcore:adder|pcarry7
- 6 - B 15 OR2 0 4 0 1 |LPM_ADD_SUB:2575|addcore:adder|pcarry8
- 3 - D 24 OR2 0 4 0 2 |LPM_ADD_SUB:2575|addcore:adder|:72
- 5 - D 24 OR2 0 4 0 1 |LPM_ADD_SUB:2575|addcore:adder|:124
- 8 - D 17 OR2 s 0 3 0 1 |LPM_ADD_SUB:2575|addcore:adder|~128~1
- 6 - B 23 OR2 s 0 3 0 1 |LPM_ADD_SUB:2575|addcore:adder|~129~1
- 7 - B 23 OR2 s 0 3 0 1 |LPM_ADD_SUB:2575|addcore:adder|~130~1
- 5 - B 15 OR2 s 0 3 0 1 |LPM_ADD_SUB:2575|addcore:adder|~131~1
- 8 - B 14 OR2 s 0 4 0 1 |LPM_ADD_SUB:2575|addcore:adder|~132~1
- 1 - B 14 OR2 s 0 4 0 1 |LPM_ADD_SUB:2575|addcore:adder|~132~2
- 8 - B 15 OR2 s 0 4 0 1 |LPM_ADD_SUB:2575|addcore:adder|~132~3
- 8 - B 20 DFFE + 0 3 0 1 f33 (:31)
- 7 - B 20 DFFE + 0 3 0 2 f32 (:32)
- 5 - B 20 DFFE + 0 2 0 3 f31 (:33)
- 2 - B 20 DFFE + 0 0 0 8 f30 (:34)
- 4 - B 07 DFFE + 0 3 0 1 m39 (:35)
- 2 - B 07 DFFE + 0 3 0 4 m38 (:36)
- 3 - B 07 DFFE + 0 3 0 4 m37 (:37)
- 3 - B 06 DFFE + 0 3 0 4 m36 (:38)
- 4 - B 06 DFFE + 0 3 0 6 m35 (:39)
- 5 - B 06 DFFE + 0 3 0 7 m34 (:40)
- 6 - B 06 DFFE + 0 0 0 8 m33 (:41)
- 5 - B 03 DFFE + 0 0 0 2 m32 (:42)
- 4 - D 22 DFFE + 0 0 0 2 m31 (:43)
- 3 - D 22 DFFE + 0 0 0 6 m30 (:44)
- 6 - C 19 DFFE + 0 3 0 4 f23 (:45)
- 3 - C 19 DFFE + 0 2 0 5 f22 (:46)
- 8 - C 19 DFFE + 0 3 0 5 f21 (:47)
- 4 - C 19 DFFE + 0 0 0 6 f20 (:48)
- 6 - B 08 DFFE + 0 3 0 1 m29 (:49)
- 8 - B 08 DFFE + 0 3 0 4 m28 (:50)
- 2 - B 08 DFFE + 0 3 0 4 m27 (:51)
- 3 - B 02 DFFE + 0 3 0 4 m26 (:52)
- 4 - B 02 DFFE + 0 3 0 4 m25 (:53)
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