library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity add8b is
port(a:in std_logic_vector(7 downto 0);
      b:in std_logic_vector(7 downto 0);
     n:out std_logic_vector(7 downto 0));
end;
architecture one of add8b is
begin
n<=a+b;
end;