Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       8/ 96(  8%)     0/ 48(  0%)     3/ 48(  6%)    7/16( 43%)      3/16( 18%)     0/16(  0%)
B:       7/ 96(  7%)     2/ 48(  4%)     0/ 48(  0%)    5/16( 31%)      4/16( 25%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      1/24(  4%)     0/4(  0%)      1/4( 25%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                         e:\edashi\sin\control.rpt
control

** EQUATIONS **

am0      : INPUT;
am1      : INPUT;
am2      : INPUT;
am3      : INPUT;
am4      : INPUT;
am5      : INPUT;
am6      : INPUT;
am7      : INPUT;
codeout  : INPUT;
fout0    : INPUT;
fout1    : INPUT;
fout2    : INPUT;
fout3    : INPUT;
fout4    : INPUT;
fout5    : INPUT;
fout6    : INPUT;
fout7    : INPUT;
q0       : INPUT;
q1       : INPUT;

-- Node name is 'dout0' 
-- Equation name is 'dout0', type is output 
dout0    =  _LC2_B10;

-- Node name is 'dout1' 
-- Equation name is 'dout1', type is output 
dout1    =  _LC6_B10;

-- Node name is 'dout2' 
-- Equation name is 'dout2', type is output 
dout2    =  _LC1_B10;

-- Node name is 'dout3' 
-- Equation name is 'dout3', type is output 
dout3    =  _LC3_B10;

-- Node name is 'dout4' 
-- Equation name is 'dout4', type is output 
dout4    =  _LC1_A19;

-- Node name is 'dout5' 
-- Equation name is 'dout5', type is output 
dout5    =  _LC5_A19;

-- Node name is 'dout6' 
-- Equation name is 'dout6', type is output 
dout6    =  _LC8_A19;

-- Node name is 'dout7' 
-- Equation name is 'dout7', type is output 
dout7    =  _LC2_A19;

-- Node name is '~282~1' 
-- Equation name is '~282~1', location is LC7_A19, type is buried.
-- synthesized logic cell 
_LC7_A19 = LCELL( _EQ001);
  _EQ001 = !codeout & !q0 &  q1
         #  am7 &  q0 & !q1;

-- Node name is ':282' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = LCELL( _EQ002);
  _EQ002 =  _LC7_A19
         #  fout7 &  q1
         #  fout7 & !q0;

-- Node name is '~297~1' 
-- Equation name is '~297~1', location is LC6_A19, type is buried.
-- synthesized logic cell 
_LC6_A19 = LCELL( _EQ003);
  _EQ003 =  fout6 & !q0 & !q1
         #  fout6 &  q0 &  q1
         #  codeout &  fout6 &  q1
         #  codeout &  fout6 & !q0;

-- Node name is ':297' 
-- Equation name is '_LC8_A19', type is buried 
_LC8_A19 = LCELL( _EQ004);
  _EQ004 =  _LC6_A19
         #  am6 &  q0 & !q1;

-- Node name is '~312~1' 
-- Equation name is '~312~1', location is LC4_A19, type is buried.
-- synthesized logic cell 
_LC4_A19 = LCELL( _EQ005);
  _EQ005 =  fout5 & !q0 & !q1
         #  fout5 &  q0 &  q1
         #  codeout &  fout5 &  q1
         #  codeout &  fout5 & !q0;

-- Node name is ':312' 
-- Equation name is '_LC5_A19', type is buried 
_LC5_A19 = LCELL( _EQ006);
  _EQ006 =  _LC4_A19
         #  am5 &  q0 & !q1;

-- Node name is '~327~1' 
-- Equation name is '~327~1', location is LC3_A19, type is buried.
-- synthesized logic cell 
_LC3_A19 = LCELL( _EQ007);
  _EQ007 =  fout4 & !q0 & !q1
         #  fout4 &  q0 &  q1
         #  codeout &  fout4 &  q1
         #  codeout &  fout4 & !q0;

-- Node name is ':327' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ008);
  _EQ008 =  _LC3_A19
         #  am4 &  q0 & !q1;

-- Node name is '~342~1' 
-- Equation name is '~342~1', location is LC8_B10, type is buried.
-- synthesized logic cell 
_LC8_B10 = LCELL( _EQ009);
  _EQ009 =  fout3 & !q0 & !q1
         #  fout3 &  q0 &  q1
         #  codeout &  fout3 &  q1
         #  codeout &  fout3 & !q0;

-- Node name is ':342' 
-- Equation name is '_LC3_B10', type is buried 
_LC3_B10 = LCELL( _EQ010);
  _EQ010 =  _LC8_B10
         #  am3 &  q0 & !q1;

-- Node name is '~357~1' 
-- Equation name is '~357~1', location is LC7_B10, type is buried.
-- synthesized logic cell 
_LC7_B10 = LCELL( _EQ011);
  _EQ011 =  fout2 & !q0 & !q1
         #  fout2 &  q0 &  q1
         #  codeout &  fout2 &  q1
         #  codeout &  fout2 & !q0;

-- Node name is ':357' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = LCELL( _EQ012);
  _EQ012 =  _LC7_B10
         #  am2 &  q0 & !q1;

-- Node name is '~372~1' 
-- Equation name is '~372~1', location is LC5_B10, type is buried.
-- synthesized logic cell 
_LC5_B10 = LCELL( _EQ013);
  _EQ013 =  fout1 & !q0 & !q1
         #  fout1 &  q0 &  q1
         #  codeout &  fout1 &  q1
         #  codeout &  fout1 & !q0;

-- Node name is ':372' 
-- Equation name is '_LC6_B10', type is buried 
_LC6_B10 = LCELL( _EQ014);
  _EQ014 =  _LC5_B10
         #  am1 &  q0 & !q1;

-- Node name is '~387~1' 
-- Equation name is '~387~1', location is LC4_B10, type is buried.
-- synthesized logic cell 
_LC4_B10 = LCELL( _EQ015);
  _EQ015 =  fout0 & !q0 & !q1
         #  fout0 &  q0 &  q1
         #  codeout &  fout0 &  q1
         #  codeout &  fout0 & !q0;

-- Node name is ':387' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ016);
  _EQ016 =  _LC4_B10
         #  am0 &  q0 & !q1;



Project Information                                  e:\edashi\sin\control.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,678K