?? div256.rpt
字號:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\edashi\am\div256.rpt
div256
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 11 LCELL s 1 0 1 0 q3out0~1
- 7 - A 21 LCELL s 1 0 1 0 q3out1~1
- 2 - C 16 LCELL s 1 0 1 0 q3out2~1
- 8 - B 12 LCELL s 1 0 1 0 q3out3~1
- 3 - A 05 LCELL s 1 0 1 0 q3out4~1
- 2 - C 04 LCELL s 1 0 1 0 q3out5~1
- 1 - A 10 LCELL s 1 0 1 0 q3out6~1
- 2 - A 17 LCELL s 1 0 1 0 q3out7~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\edashi\am\div256.rpt
div256
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 2/ 48( 4%) 1/ 48( 2%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 1/ 96( 1%) 1/ 48( 2%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\edashi\am\div256.rpt
div256
** EQUATIONS **
q38 : INPUT;
q39 : INPUT;
q310 : INPUT;
q311 : INPUT;
q312 : INPUT;
q313 : INPUT;
q314 : INPUT;
q315 : INPUT;
-- Node name is 'q3out0~1'
-- Equation name is 'q3out0~1', location is LC1_B11, type is buried.
-- synthesized logic cell
_LC1_B11 = LCELL( q38);
-- Node name is 'q3out0'
-- Equation name is 'q3out0', type is output
q3out0 = _LC1_B11;
-- Node name is 'q3out1~1'
-- Equation name is 'q3out1~1', location is LC7_A21, type is buried.
-- synthesized logic cell
_LC7_A21 = LCELL( q39);
-- Node name is 'q3out1'
-- Equation name is 'q3out1', type is output
q3out1 = _LC7_A21;
-- Node name is 'q3out2~1'
-- Equation name is 'q3out2~1', location is LC2_C16, type is buried.
-- synthesized logic cell
_LC2_C16 = LCELL( q310);
-- Node name is 'q3out2'
-- Equation name is 'q3out2', type is output
q3out2 = _LC2_C16;
-- Node name is 'q3out3~1'
-- Equation name is 'q3out3~1', location is LC8_B12, type is buried.
-- synthesized logic cell
_LC8_B12 = LCELL( q311);
-- Node name is 'q3out3'
-- Equation name is 'q3out3', type is output
q3out3 = _LC8_B12;
-- Node name is 'q3out4~1'
-- Equation name is 'q3out4~1', location is LC3_A5, type is buried.
-- synthesized logic cell
_LC3_A5 = LCELL( q312);
-- Node name is 'q3out4'
-- Equation name is 'q3out4', type is output
q3out4 = _LC3_A5;
-- Node name is 'q3out5~1'
-- Equation name is 'q3out5~1', location is LC2_C4, type is buried.
-- synthesized logic cell
_LC2_C4 = LCELL( q313);
-- Node name is 'q3out5'
-- Equation name is 'q3out5', type is output
q3out5 = _LC2_C4;
-- Node name is 'q3out6~1'
-- Equation name is 'q3out6~1', location is LC1_A10, type is buried.
-- synthesized logic cell
_LC1_A10 = LCELL( q314);
-- Node name is 'q3out6'
-- Equation name is 'q3out6', type is output
q3out6 = _LC1_A10;
-- Node name is 'q3out7~1'
-- Equation name is 'q3out7~1', location is LC2_A17, type is buried.
-- synthesized logic cell
_LC2_A17 = LCELL( q315);
-- Node name is 'q3out7'
-- Equation name is 'q3out7', type is output
q3out7 = _LC2_A17;
Project Information e:\edashi\am\div256.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 18,005K
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