library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity div256 is
port(q3:in std_logic_vector(15 downto 0);
     q3out:out std_logic_vector(7 downto 0));
end;
architecture one of div256 is
begin
q3out(7)<=q3(15);
q3out(6)<=q3(14);
q3out(5)<=q3(13);
q3out(4)<=q3(12);
q3out(3)<=q3(11);
q3out(2)<=q3(10);
q3out(1)<=q3(9);
q3out(0)<=q3(8);
end;